CS8900A
Crystal LAN™ ISA Ethernet Controller
3.2 ISA Bus Interface
3.2.3 Interrupt Request Signals
The CS8900A provides a direct interface to ISA
buses running at clock rates from 8 to 11 MHz. Its
on-chip bus drivers are capable of delivering
24 mA of drive current, allowing the CS8900A to
drive the ISA bus directly, without added external
"glue logic".
The CS8900A has four interrupt request output
pins that can be connected directly to any four of
the ISA bus Interrupt Request signals. Only one in-
terrupt output is used at a time. It is selected during
initialization by writing the interrupt number (0 to
3) into PacketPage Memory base + 0022h. Unused
interrupt request pins are placed in a high-imped-
ance state. The selected interrupt request pin goes
high when an enabled interrupt is triggered. The
pin goes low after the Interrupt Status Queue (ISQ)
is read as all 0’s (see Section 5.1 on page 79 for a
description of the ISQ).
The CS8900A is optimized for 16-bit data trans-
fers, operating in either Memory space, I/O space,
or as a DMA slave.
Note that ISA-bus operation below 8 MHz should
use the CS8900A’s Receive DMA mode to mini-
mize missed frames. See Section 5.4 on page 90 for
a description of Receive DMA operation.
Table 1 presents one possible way of connecting
the interrupt request pins to the ISA bus that utiliz-
es commonly available interrupts and facilitates
board layout.
3.2.1 Memory Mode Operation
When configured for Memory Mode operation, the
CS8900A’s internal registers and frame buffers are
mapped into a contiguous 4-Kbyte block of host
memory, providing the host with direct access to
the CS8900A’s internal registers and frame buff-
ers. The host initiates Read operations by driving
the MEMR pin low and Write operations by driv-
ing the MEMW pin low.
CS8900A Interrupt
Request Pin
ISA Bus
Interrupt
PacketPage
base + 0022h
IRQ5
IRQ10
IRQ11
IRQ12
0003h
0000h
0001h
0002h
INTRQ3 (Pin 35)
INTRQ0 (Pin 32)
INTRQ1 (Pin 31)
INTRQ2 (Pin 30)
Table 1. Interrupt Assignments
For additional information about Memory Mode,
see Section 4.9 on page 74.
3.2.4 DMA Signals
The CS8900A interfaces directly to the host DMA
controller to provide DMA transfers of receive
frames from CS8900A memory to host memory.
The CS8900A has three pairs of DMA pins that can
be connected directly to the three 16-bit DMA
channels of the ISA bus. Only one DMA channel is
used at a time. It is selected during initialization by
writing the number of the desired channel (0, 1 or
2) into PacketPage Memory base + 0024h. Unused
3.2.2 I/O Mode Operation
When configured for I/O Mode operation, the
CS8900A is accessed through eight, 16-bit I/O
ports that are mapped into sixteen contiguous I/O
locations in the host system’s I/O space. I/O Mode
is the default configuration for the CS8900A and is
always enabled.
For an I/O Read or Write operation, the AEN pin
must be low, and the 16-bit I/O address on the ISA DMA pins are placed in a high-impedance state.
System Address bus (SA0 - SA15) must match the
address space of the CS8900A. For a Read, IOR
must be low, and for a Write, IOW must be low.
The selected DMA request pin goes high when the
CS8900A has received frames to transfer to the
host memory via DMA. If the DMABurst bit (reg-
ister 17, BusCTL, Bit B) is clear, the pin goes low
after the DMA operation is complete. If the
For additional information about I/O Mode, see
Section 4.10 on page 76.
CIRRUS LOGIC PRODUCT DATA SHEET
18
DS271PP3
CIRRUS [ CIRRUS LOGIC ]
