CS8900A
Crystal LAN™ ISA Ethernet Controller
Bit 7), and then set it when the changes are com-
plete.
Register 7, TxCFG
Operation
Bit
Bit Name
6
Loss-of-
CRSiE
When set, there is an interrupt
whenever the CS8900A fails to
detect Carrier Sense after trans-
mitting the preamble (applies to
the AUI only).
5.7.4 Enabling CRC Generation and Padding
Whenever the host issues a Transmit Request com-
mand, it must indicate whether or not the Cyclic
Redundancy Check (CRC) value should be ap-
pended to the transmit frame, and whether or not
pad bits should be added (if needed). Table 33 de-
scribes how to configure the CS8900A for CRC
generating and padding.
7
8
SQErroriE When set, there is an interrupt
whenever there is an SQE error.
TxOKiE
When set, there is an interrupt
whenever a frame is transmitted
successfully..
9
Out-of-
windowiE
When set, there is an interrupt
whenever a late collision is
detected.
Register 9, TxCMD
Inhibit TxPad
CRC Dis
(Bit C) (Bit D)
Operation
A
JabberiE
When set, there is an interrupt
whenever there is a jabber condi-
tion.
0
1
0
1
0
0
1
1
Pad to 64 bytes if necessary
(including CRC).
B
F
AnycolliE
16colliE
When set, there is an interrupt
whenever there is a collision.
Send a runt frame if specified
length less than 60 bytes.
When set, there is an interrupt
whenever the CS8900A attempts
to transmit a single frame 16
times.
Pad to 60 bytes if necessary (with-
out CRC).
Send runt if specified length less
than 64. The CS8900A will not
transmit a frame that is less than 3
bytes.
Table 31. Transmitting Interrupt Configuration
Register B, BufCFG
Bit
Bit Name
Operation
Table 33. CRC and Paddling Configuration
8
Rdy4TxiE When set, there is an interrupt
whenever buffer space becomes
available for a transmit frame
5.7.5 Individual Packet Transmission
Whenever the host has a packet to transmit, it must
issue a Transmit Request to the CS8900A consist-
ing of the following three operations in the exact
order shown:
(used with a Transmit Request).
9
TxUnder
runiE
When set, there is an interrupt
whenever ther CS8900A runs out
of data after transmit has started.
C
TxCol
OvfloiE
When set, there is an interrupt
whenever the TxCol counter
overflows.
1) The host must write a Transmit Command to
the TxCMD register (PacketPage base +
0144h). The contents of the TxCMD register
may be read back from the TxCMD register
(Register 9).
Table 32. Transmit Interrupt Configuration
If the host chooses to change bits in the LineCTL
register after initialization, the ModBackoffE bit
and any receive related bit (LoRxSquelch, SerRx-
ON) may be changed at any time. However, the
Auto AUI/10BT and AUIonly bits should not be
changed while the SerTxON bit is set. If any of
these three bits are to be changed, the host should
first clear the SerTxON bit (Register 13, LineCTL,
2) The host must write the frame’s length to the
TxLength register (PacketPage base + 0146h).
3) The host must read the BusST register (Regis-
ter 18)
The information written to the TxCMD register
tells the CS8900A how to transmit the next frame.
CIRRUS LOGIC PRODUCT DATA SHEET
100
DS271PP3
CIRRUS [ CIRRUS LOGIC ]
