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CS8900A-IQ 参数 Datasheet PDF下载

CS8900A-IQ图片预览
型号: CS8900A-IQ
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ ISA Ethernet Controller  
Figure 26 shows the steps the CS8900A goes  
frame to be transferred. Instead, the oldest noncom-  
through in determining when to automatically mitted frame in the on-chip buffer is the first frame  
switch to DMA.  
to use DMA. When DMA begins, any pending Rx-  
Event reports in the Interrupt Status Queue are dis-  
carded because the host cannot process those  
events until the corresponding frames have been  
completely DMAed.  
Packet Received  
Auto-Switch DMA works only on entire received  
frames. The CS8900A does not use Auto-Switch  
DMA to transfer partial frames. Also, when a frame  
has been committed (see Section 5.2.5 on page 84),  
the CS8900A will not switch to DMA mode until  
the committed frame has been transferred com-  
pletely or skipped.  
Frame  
Passed the  
DA filter?  
No  
Frame  
Discarded  
Yes  
After a complete frame has been moved to host  
memory, the CS8900A updates the DMA Start-of-  
Frame register (PacketPage base + 0126h), the  
DMA Frame Count register (PacketPage base +  
0128h), and the DMA Byte Count register, then  
sets the RxDMAFrame bit (Register C, BufEvent,  
bit 7). If RxDMAiE (Register B, BufCFG, bit 7) is  
set, a corresponding interrupt occurs.  
Yes  
All Frames  
use DMA  
RxDMA only  
Bit=1  
No  
More  
Buffer Space  
Available?  
Yes  
Frame Buffered  
in On-chip RAM  
5.5.4 DMA Channel Speed vs. Missed Frames  
No  
When the CS8900A starts DMA, the entire oldest,  
noncommitted frame must be placed in host mem-  
ory before on-chip buffer space will be freed for the  
next incoming frame. If the oldest frame is relative-  
ly large, and the next incoming frame also large,  
the incoming frame may be missed, depending on  
the speed of the DMA channel. If this happens, the  
CS8900A will increment the RxMiss counter (Reg-  
ister 10) and clear any event reports (RxEvent and  
BufEvent) associated with the missed frame.  
No  
Auto-Switch  
DMA Disabled  
AutoRxDMA  
Bit=1?  
Yes  
Auto-Switch to DMA  
Figure 26. Conditions for Switching to DMA  
5.5.5 Exit From DMA  
Whenever the CS8900A automatically enters  
DMA, at least one complete frame is already stored  
in the on-chip buffer. Because frames are trans-  
ferred to the host in the same order as received (first  
in, first out), the beginning of the received frame  
that triggered the switch to DMA is not the first  
When the CS8900A has activated receive DMA, it  
remains in DMA mode until all of the following are  
true:  
The host processes all RxEvent and BufEvent  
reports pending in the ISQ.  
CIRRUS LOGIC PRODUCT DATA SHEET  
DS271PP3  
95