CS8900A
Crystal LAN™ ISA Ethernet Controller
Register 3, RxCFG
Receive Frame
Bit
Bit Name
Operation
7
StreamE
When set, Stream Transfer
enabled.
Destination
Address Filter
9
RxDMAonly
When set, DMA slave opera-
tion used for all receive
frames.
Check:
- PromiscuousA?
- IAHashA?
- MulticastA?
- IndividualA?
- BroadcastA?
A
B
AutoRX DMAE When set, Auto-Switch DMA
enabled.
BufferCRC
When set, the received CRC
is buffered.
Register 17, BusCTL
Pass
DA Filter?
No
Bit
Bit Name
Operation
Discard Frame
B
DMABurst
When set, DMA operations
hold the bus for up to approx-
imately 28 µs. When clear,
DMA operations are continu-
ous.
Yes
Generate Early
Interrupts if Enabled
(see next figure)
D
RxDMAsize
When set, DMA buffer size is
64 Kbytes. When clear, DMA
buffer size is 16 Kbytes.
Acceptance Filter
Check:
Table 22. Receive Frame Pre-Processing
- RxOKA?
- ExtradataA?
- RuntA?
5.2.3 Receive Frame Pre-Processing
The CS8900A pre-processes all receive frames us-
ing a four step process:
- CRCerrorA?
1) Destination Address filtering;
2) Early Interrupt Generation;
3) Acceptance filtering; and,
4) Normal Interrupt Generation.
Pass
Accept.
Filter?
Yes
No
Status of receive
frame reported in
RxEvent register,
frame discarded.
Status of receive
frame reported in
RxEvent register,
frame accepted
into on-chip RAM
Figure 21 provides a diagram of frame pre-process-
ing.
5.2.3.1 Destination Address Filtering
Generate Interrupts
All incoming frames are passed through the Desti-
nation Address filter (DA filter). If the frame’s DA
passes the DA filter, the frame is passed on for fur-
ther pre-processing. If it fails the DA filter, the
frame is discarded. See Section 5.3 on page 87 for
a more detailed description of DA filtering.
Check:
- RxOKiE?
- ExtradataiE?
- CRCerroriE?
- RuntiE?
- RxDMAiE?
Pre-Processing
Complete
Figure 21. Receive Frame Pre-Processing
CIRRUS LOGIC PRODUCT DATA SHEET
DS271PP3
83
CIRRUS [ CIRRUS LOGIC ]
