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CS5014-BL28 参数 Datasheet PDF下载

CS5014-BL28图片预览
型号: CS5014-BL28
PDF下载: 下载PDF文件 查看货源
内容描述: 16 , 14和12位,自校准的A / D转换器 [16, 14 & 12-Bit, Self-Calibrating A/D Converters]
分类和应用: 转换器
文件页数/大小: 46 页 / 401 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5012A  
CS5012A ANALOG CHARACTERISTICS (continued)  
CS5012A-K  
CS5012A-B  
CS5012-T  
Parameter*  
Min Typ Max Min Typ Max Min Typ Max Units  
Specified Temperature Range  
Analog Input  
0 to +70  
-40 to +85  
-55 to +125  
°C  
Aperture Time  
25  
25  
25  
ns  
ps  
Aperture Jitter  
100  
100  
100  
Input Capacitance  
Unipolar Mode CS5012  
CS5012A  
(Note 4)  
275 375  
103 137  
165 220  
275 375  
103 137  
165 220  
275 375  
103 137  
165 220  
pF  
pF  
pF  
pF  
Bipolar Mode CS5012  
CS5012A  
72  
96  
72  
96  
72  
96  
Conversion & Throughput  
Conversion Time -7 (Notes 5 and 6)  
-12  
7.2  
12.25  
7.2  
12.25  
µs  
µs  
12.25  
Acquisition Time  
-7  
-12  
(Note 6)  
2.5  
3.0 3.75  
2.8  
2.5  
3.0 3.75  
2.8  
µs  
µs  
3.0 3.75  
Throughput  
-7  
-12  
(Note 6) 100  
62.5  
100  
62.5  
kHz  
kHz  
62.5  
Power Supplies  
DC Power Supply Currents  
I +  
(Note 7)  
12  
-12  
3
6
-3  
19  
-19  
6
7.5  
-6  
12  
-12  
3
6
-3  
19  
-19  
6
7.5  
-6  
12  
-12  
3
19  
-19  
6
mA  
mA  
mA  
mA  
mA  
A
I -  
A
D
(CS5012)  
(CS5012A)  
I +  
I +  
D
I -  
-3  
-6  
D
Power Dissipation  
(Note 7)  
(Note 8)  
150 250  
150 250  
150 250  
mW  
Power Supply Rejection  
Positive Supplies  
84  
84  
84  
84  
84  
84  
dB  
dB  
Negative Supplies  
Notes: 4. Applies only in track mode. When converting or calibrating, input capacitance will not exceed 15 pF.  
5. Measured from falling transition on HOLD to falling transition on EOC.  
6. Conversion, acquisition, and throughput times depend on CLKIN, sampling, and calibration conditions.  
The numbers shown assume sampling and conversion is synchronized with the CS5012A/14/16 ’s  
conversion clock, interleave calibrate is disabled, and operation is from the full-rated, external clock.  
Refer to the section Conversion Time/Throughput for a detailed discussion of conversion timing.  
7. All outputs unloaded. All inputs CMOS levels.  
8. With 300 mV p-p, 1 kHz ripple applied to each analog supply separately in bipolar mode. Rejection  
improves by 6 dB in the unipolar mode to 90 dB. Figure 13 shows a plot of typical power supply  
rejection versus frequency.  
DS14F6  
2-9