CS4923/4/5/6/7/8/9
SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT
(TA = 25 °C; VA, VD = 3.3 V ±5%; measurements performed under static conditions.)
Parameter
Symbol
Min
Max
Unit
MCLK period
(Note 24)
Tmclk
40
-
ns
MCLK duty cycle
(Note 24)
(Note 25)
40
40
60
-
%
SCLK period for Master or Slave mode
Tsclk
ns
SCLK duty cycle for Master or Slave mode
(Note 25)
45
55
%
Master Mode
(Note 25,26)
SCLK delay from MCLK rising edge, MCLK as an input
SCLK delay from MCLK rising edge, MCLK as an output
Tsdmi
Tsdmo
Tlrds
15
10
10
10
ns
ns
ns
ns
–5
LRCLK delay from SCLK transition
AUDATA2–0 delay from SCLK transition
Slave Mode
(Note 27)
(Note 27)
(Note 28)
Tadsm
Time from active edge of SCLKN1(2) to LRCLKN1(2) transition
Time from LRCLKN1(2) transition to SCLKN1(2) active edge
Tstlr
Tlrts
10
10
-
-
ns
ns
ns
AUDATA2–0 delay from SCLK transition
(Note 27,29)
Tadss
15
Notes: 24. MCLK can be an input or an output. These specifications apply for both cases.
25. Master mode timing specifications are characterized, not production tested.
26. Master mode is defined as the CS4923 driving both SCLK and LRCLK. When MCLK is an input, it is
divided to produce SCLK and LRCLK.
27. This timing parameter is defined from the non-active edge of SCLK. The active edge of SCLK is the
point at which the data is valid.
28. Slave mode is defined as SCLK and LRCLK being driven by an external source.
29. This specification is characterized, not production tested.
18
DS262F2
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