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CS4351-CZZ 参数 Datasheet PDF下载

CS4351-CZZ图片预览
型号: CS4351-CZZ
PDF下载: 下载PDF文件 查看货源
内容描述: 192 kHz立体声DAC 2 Vrms的线路输出 [192 kHz STEREO DAC WITH 2 Vrms LINE OUT]
分类和应用: 转换器数模转换器光电二极管
文件页数/大小: 41 页 / 1097 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4351  
1. PIN DESCRIPTION  
20  
19  
18  
1
SDIN  
SCLK  
LRCK  
MCLK  
VD  
VL  
2
AMUTEC  
AOUTA  
VA_H  
GND  
AOUTB  
BMUTEC  
VQ  
3
4
17  
16  
15  
14  
13  
12  
5
6
GND  
7
DIF1(SCL/CCLK)  
DIF0(SDA/CDIN)  
DEM(AD0/CS)  
RST  
8
9
VBIAS  
VA  
10  
11  
Pin Name  
SDIN  
#
1
2
3
Pin Description  
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.  
Serial Clock (Input) - Serial clock for the serial audio interface.  
SCLK  
LRCK  
Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial  
audio data line.  
MCLK  
VD  
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.  
Digital Power (Input) - Positive power supply for the digital section.  
Ground (Input) - Ground reference.  
4
5
GND  
6
16  
Reset (Input) - Powers down device and resets all internal resisters to their default settings when  
enabled.  
RST  
10  
VA  
11 Low Voltage Analog Power (Input) - Positive power supply for the analog section.  
Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.  
VBIAS  
VQ  
12  
13 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.  
17 High Voltage Analog Power (Input) - Positive power supply for the analog section.  
VA_H  
VL  
Serial Audio Interface Power (Input) - Positive power for the serial audio interface  
Mute Control (Output) - Control signal for optional mute circuit.  
20  
BMUTEC  
AMUTEC  
14  
19  
AOUTB  
AOUTA  
Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Characteris-  
tics table.  
15  
18  
Control Port  
Definitions  
SCL/CCLK  
SDA/CDIN  
Serial Control Port Clock (Input) - Serial clock for the control port interface.  
Serial Control Data (Input/Output) - Input/Output for I2C data. Input for SPI data.  
7
8
Address Bit 0 / Chip Select (Input) - Chip address bit in I2C Mode. Control Port enable in SPI mode.  
AD0/CS  
9
Stand-Alone  
Definitions  
DIF0  
DIF1  
Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial  
Clock, and Serial Audio Data.  
8
7
DEM  
9
De-emphasis (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for 44.1 kHz  
sample rates  
6
DS566PP2