CS4344/5/6/8
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
Parameters
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate
(Note 11)
All MCLK/LRCK ratios combined
256x, 384x, 1024x
256x, 384x
512x, 768x
1152x
128x, 192x
64x, 96x
128x, 192x
Fs
Symbol
Min
0.512
45
2
2
84
42
30
50
100
168
45
t
sclkl
t
sclkh
t
slrd
t
slrs
t
sdlrs
t
sdh
(Note 12)
(Note 13)
t
sclkw
t
sclkr
t
sdlrs
t
sdh
t
sdh
20
20
45
20
20
20
20
-
10 9
----------------
-
SCLK
Typ
-
-
Max
50
55
200
50
134
67
34
100
200
200
Units
MHz
%
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
%
ns
ns
%
ns
ns
ns
ns
%
ns
µs
ns
ns
ns
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Duty Cycle
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
SCLK Period
SCLK rising to LRCK edge
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
MCLK / LRCK =1152, 1024, 512, 256, 128, or 64
SCLK rising to SDIN hold time
MCLK / LRCK = 768, 384, 192, or 96
50
-
tsclkw
-----------------
-
2
50
-
-
50
-
-
-
-
55
-
-
55
-
-
-
-
-
-
-
-
-
-
-
10
9
--------------------- + 10
-
(
512
)Fs
10
9
--------------------- + 15
-
(
512
)Fs
10
9
--------------------- + 15
-
(
384
)Fs
-
-
-
Notes: 11. Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on
12. In Internal SCLK Mode, the Duty Cycle must be 50%
+/−
1/2 MCLK Period.
13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on part type and
MCLK/LRCK ratio. (See figures 7-9)
DS613PP2
9
CIRRUS [ CIRRUS LOGIC ]
