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CS4297A-JQEP 参数 Datasheet PDF下载

CS4297A-JQEP图片预览
型号: CS4297A-JQEP
PDF下载: 下载PDF文件 查看货源
内容描述: [Consumer Circuit, PQFP48, 9 X 9 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-022, TQFP-48]
分类和应用: 解码器编解码器
文件页数/大小: 46 页 / 897 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4297  
CrystalClear™ SoundFusion™ Audio Codec ’97  
Vrefout  
to via  
To +5VA  
390 pF  
NPO  
1 µF  
0.1 µF  
Y5V  
To +5VA  
AFLT2  
AFLT1  
AVss1  
AVdd1  
REFFLT  
0.1 µF  
Y5V  
To Analog  
Ground  
AVdd2  
To Analog  
Ground  
AVss2  
Analog Ground  
DVss1  
Pin 1  
0.1 µF  
Y5V  
DVdd1  
DVdd2  
To +5VD  
DVss2  
0.1 µF  
Y5V  
To +5VD  
To Digital Ground  
Figure 10. Suggested Layout for the CS4297  
ed to the digital ground plane and kept separate  
from the analog ground connections of the CS4297  
and any other external analog circuitry.  
GROUNDING AND LAYOUT  
Figure 10 is the suggested layout for the CS4297.  
The decoupling capacitors should be located phys-  
ically as close to the pins as possible. Also note the  
routing of the REFFLT decoupling capacitors and  
the isolation of that ground strip.  
It is also recommended that the common connec-  
tion point between the two ground planes (required  
to maintain a common ground voltage potential) be  
located near the CS4297 just under the digital  
ground connections (vias). The AC-Link digital in-  
terface connection traces should be routed such that  
digital ground plane lies underneath these signals  
(on the internal ground layer) from the AC’97 Con-  
troller continuously to the CS4297.  
It is strongly recommended that the device be locat-  
ed on a locally separate analog ground plane. This  
analog ground plane is used to keep noise from dig-  
ital ground return currents from modulating the  
CS4297’s ground potential and degrading perfor-  
mance. The digital ground pins should be connect-  
DS242F5  
33  
 
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