CS4297A
CS4297A
3.2
AC-Link Audio Input Frame
In the serial data input frame, data is passed on the SDATA_IN pin from the CS4297A to the AC ’97 con-
troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 13 illus-
trates the serial port timing.
The PCM capture data from the CS4297A is shifted out MSB first in the most significant 18 bits of each
slot. The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from the
AC ’97 Controller that is less than 18 bits wide, the controller should dither and round or just round (but
not truncate) to the desired bit depth.
Bits that are reserved or not implemented in the CS4297A will always be returned ‘cleared’.
3.2.1 Serial Data Input Slot Tag Bits (Slot 0)
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Codec Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10
Ready Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
0
0
0
0
0
Codec Ready
The Codec Ready bit indicates the readiness of the CS4297A AC-link. Immediately after a
Cold Reset this bit will be ‘clear’. Once the CS4297A clocks and voltages are stable, this bit
will be ‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be attempted
by the controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref,
or any other analog function. Those must be checked in the Powerdown Control/Status Reg-
ister (Index 26h) by the controller before any access is made to the mixer registers. Any ac-
cesses to the CS4297A while Codec Ready is ‘clear’ are ignored.
Slot 1 Valid
When ‘set’, the Slot 1 Valid bit indicates Slot 1 contains a valid read back address.
When ‘set’, the Slot 2 Valid bit indicates Slot 2 contains valid register read data.
Slot 2 Valid
Slot [3:10] Valid
When ‘set’, the Slot [3:10] Valid bits indicate Slot [3:10] contains valid capture data from the
CS4297A ADCs. Only if a Slot [3:10] Valid bit is ‘set’ will the corresponding input slot contain
valid data.
3.2.2 Status Address Port (Slot 1)
Bit 19 18
17
16
15
14
13
12
11
0
10
0
9
8
7
6
5
4
3
2
1
0
0
RI6 RI5 RI4 RI3 RI2 RI1 RI0
0
0
0
0
0
0
0
Reserved
RI[6:0]
Register Index. The RI[6:0] bits echo the AC ’97 register address when a register read has
been requested in the previous frame. The CS4297A will only echo the register index for a
read access. Write accesses will not return valid data in Slot 1.
16
16
DS318PP6
CIRRUS [ CIRRUS LOGIC ]
