Function:
When enabled, these bits will invert the signal polarity of their respective channels.
7.13 STATUS (ADDRESS 19H) (READ ONLY)
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
CLK Error
ADC3_OVFL
ADC2_OVFL
ADC1_OVFL
For all bits in this register, a “1” means the associated error condition has occurred at least once since the register
was last read. A”0” means the associated error condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always
be “0” in this register.
7.13.1 CLOCK ERROR (CLK ERROR)
Default = x
Function:
Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes ac-
tive during the error condition. See “System Clocking” on page 33 for valid clock ratios.
7.13.2 ADC OVERFLOW (ADCX_OVFL)
Default = x
Function:
Indicates that there is an over-range condition anywhere in the CS42438 ADC signal path of each of
the associated ADC’s.
7.14 STATUS MASK (ADDRESS 1AH)
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
CLK Error_M ADC3_OVFL_M ADC2_OVFL_M ADC1_OVFL_M
Default = 0000
Function:
The bits of this register serve as a mask for the error sources found in the register “Status (address
19h) (Read Only)” on page 50. If a mask bit is set to 1, the error is unmasked, meaning that its occur-
rence will affect the status register. If a mask bit is set to 0, the error is masked, meaning that its oc-
currence will not affect status register. The bit positions align with the corresponding bits in the Status
register.
50
DS646PP2
CIRRUS [ CIRRUS LOGIC ]
