1 PIN DESCRIPTION - SOFTWARE MODE
52 51 50 49 48 47 46 45 44 43 42 41 40
SCL/CCLK
SDA/CDOUT
AD0/CS
AD1/CDIN
RST
AIN1+
AIN1-
VA
39
38
1
2
3
37
36
35
34
33
VQ
4
AGND
N.C.
5
VLC
6
CS42432
FS
N.C.
7
VD
N.C.
8
32
31
30
29
28
27
DGND
VLS
N.C.
9
AOUT6-
AOUT6+
AOUT5+
10
11
12
SCLK
MCLK
ADC_SDOUT
AOUT5-
13
14 15 16 17 18 19 20 21 22 23 24 25 26
Pin Name
SCL/CCLK
SDA/CDOUT
#
1
2
3
Pin Description
Serial Control Port Clock (Input) - Serial clock for the control port interface.
Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Output for SPI data.
Address Bit [0]/ Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select
AD0/CS
the chip in SPI mode.
4
5
Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I2C Mode. Input for SPI data.
AD1/CDIN
RST
Reset (Input) - The device enters a low power mode and all internal registers are reset to their
default settings when low.
VLC
6
Control Port Power (Input) - Determines the required signal level for the control port interface.
See “Digital I/O Pin Characteristics” on page 7.
FS
7
8
Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format.
Digital Power (Input) - Positive power supply for the digital section.
VD
DGND
VLS
9,18 Digital Ground (Input) -
10 Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter-
faces. See “Digital I/O Pin Characteristics” on page 7.
SCLK
11
Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256xFs.
MCLK
12 Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters.
13 Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data.
14 DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data.
ADC_SDOUT
DAC_SDIN
AUX_LRCK
15 Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active
on the Auxiliary serial audio data line.
6
DS673PP2
CIRRUS [ CIRRUS LOGIC ]
