CS42432
7.4
Functional Mode (Address 03h)
7
6
5
4
3
2
1
0
MFreq2
MFreq1
MFreq0
Reserved
Reserved
Reserved
Reserved
Reserved
7.4.1
MCLK Frequency (MFREQ[2:0])
Default = 000
Function:
Sets the appropriate frequency for the supplied MCLK. For TDM operation, SCLK must equal 256Fs.
MCLK can be equal to or greater than SCLK.
Ratio (xFs)
MFreq2
MFreq1
MFreq0
Description
SSM
256
384
512
768
DSM
N/A
N/A
256
384
512
QSM
N/A
N/A
N/A
N/A
256
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
1.0290 MHz to 12.8000 MHz
1.5360 MHz to 19.2000 MHz
2.0480 MHz to 25.6000 MHz
3.0720 MHz to 38.4000 MHz
4.0960 MHz to 51.2000 MHz
1024
Table 5. MCLK Frequency Settings
7.5
MISCELLANEOUS CONTROL (Address 04h)
7
6
5
4
3
2
1
0
FREEZE
AUX_DIF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7.5.1
Freeze Controls (FREEZE)
Default = 0
Function:
This function will freeze the previous settings of, and allow modifications to be made to the channel mutes,
the DAC and ADC Volume Control/Channel Invert registers without the changes taking effect until the
FREEZE is disabled. To have multiple changes in these control port registers take effect simultaneously,
enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
7.5.2
Auxiliary Digital Interface Format (AUX_DIF)
Default = 0
0 - Left Justified
1 - I²S
Function:
This bit selects the digital interface format used for the AUX Serial Port. The required relationship between
the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options
are detailed in Figures 16-17.
DS673F1
41
CIRRUS [ CIRRUS LOGIC ]
