CS42432
FS is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data sample
and must be held valid for at least 1 SCLK period.
Note: The ADC does not meet the timing requirements for proper operation in Quad-Speed Mode.
256 clks
Bit or Word Wide
FS
SCLK
MSB
LSB
LSB MSB
MSB
LSB MSB
LSB MSB
LSB MSB
AOUT2
LSB MSB
AOUT3
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
DAC_SDIN
AOUT1
32 clks
AOUT4
32 clks
AOUT5
32 clks
AOUT6
32 clks
-
-
32 clks
32 clks
32 clks
32 clks
LSB MSB
LSB MSB
LSB MSB
ADC_SDOUT
AIN1
AIN2
AIN3
AIN4
-
-
AUX1
AUX2
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Figure 13. TDM Serial Audio Format
5.5.2
I/O Channel Allocation
Interface
Format
TDM
TDM
Analog Output/Input Channel Allocation
from/to Digital I/O
Digital Input/Output
DAC_SDIN
AOUT 1,2,3,4,5,6
AIN 1,2,3,4 (2 additional channels from AUX_SDIN)
Table 4. Serial Audio Interface Channel Allocations
ADC_SDOUT
5.6
AUX Port Digital Interface Formats
These serial data lines are used when supporting the TDM Mode of operation with an external ADC or
S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will operate
at 64xFs, where Fs is equal to the ADC sample rate (FS on the TDM interface). If the AUX_SDIN signal is
not being used, it should be tied to AGND via a pull-down resistor.
5.6.1
Hardware Mode
The AUX port will only operate in the Left-Justified digital interface format and supports bit depths ranging
from 16 to 24 bits (see Figure 17 on page 34 for timing relationship between AUX_LRCK and
AUX_SCLK).
5.6.2
5.6.3
Software Mode
The AUX port will operate in either the Left-Justified or I²S digital interface format with bit depths ranging
from 16 to 24 bits. Settings for the AUX port are made through the register “Miscellaneous Control (Ad-
dress 04h)” on page 41.
I²S
AUX_LRCK
Left Channel
Right Channel
AUX_SCLK
AUX_SDIN
M SB
LS B
M SB
LS B
MSB
AUX2
AUX1
Figure 14. AUX I²S Format
32
DS673F1
CIRRUS [ CIRRUS LOGIC ]
