CS42428
6.7 Clock Control (address 06h) ........................................................................................................... 48
6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ....................................................................... 49
6.9 Clock Status (address 08h) (Read Only) ........................................................................................ 50
6.10 Volume Transition Control (address 0Dh) .................................................................................... 51
6.11 Channel Mute (address 0Eh) ........................................................................................................ 52
6.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h) ...................................... 53
6.13 Channel Invert (address 17h) ....................................................................................................... 53
6.14 Mixing Control Pair 1 (Channels A1 & B1)(address 18h)
Mixing Control Pair 2 (Channels A2 & B2)(address 19h)
Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah)
Mixing Control Pair 4 (Channels A4 & B4)(address 1Bh) ............................................................ 53
6.15 ADC Left Channel Gain (address 1Ch) ........................................................................................ 55
6.16 ADC Right Channel Gain (address 1Dh) ...................................................................................... 55
6.17 Interrupt Control (address 1Eh) .................................................................................................... 55
6.18 Interrupt Status (address 20h) (Read Only) ................................................................................. 56
6.19 Interrupt Mask (address 21h) ....................................................................................................... 57
6.20 Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h) ............................................................................................... 57
6.21 Mutec Pin Control (address 28h) .................................................................................................. 57
6.22 General-Purpose Pin Control (addresses 29h to 2Fh) ................................................................. 58
7. PARAMETER DEFINITIONS ................................................................................................................ 60
8. APPENDIX A: EXTERNAL FILTERS ................................................................................................... 61
8.1 ADC Input Filter .............................................................................................................................. 61
8.2 DAC Output Filter ........................................................................................................................... 61
9. APPENDIX B: PLL FILTER .................................................................................................................. 62
9.1 External Filter Components ............................................................................................................ 62
9.1.1 General .................................................................................................................................. 62
9.1.2 Capacitor Selection ............................................................................................................... 62
9.1.3 Circuit Board Layout .............................................................................................................. 63
10. APPENDIX C: ADC FILTER PLOTS .................................................................................................. 64
11. APPENDIX D: DAC FILTER PLOTS .................................................................................................. 66
12. PACKAGE DIMENSIONS ............................................................................................................... 70
THERMAL CHARACTERISTICS .......................................................................................................... 70
13. ORDERING INFORMATION .............................................................................................................. 71
14. REFERENCES .................................................................................................................................... 71
15. REVISION HISTORY ......................................................................................................................... 72
LIST OF FIGURES
Figure 1.Serial Audio Port Master Mode Timing ....................................................................................... 11
Figure 2.Serial Audio Port Slave Mode Timing ......................................................................................... 11
Figure 3.Control Port Timing - I²C Format ................................................................................................. 12
Figure 4.Control Port Timing - SPI Format ................................................................................................ 13
Figure 5.Typical Connection Diagram ....................................................................................................... 18
Figure 6.Typical Connection Diagram using the PLL ................................................................................ 19
Figure 7.Full-Scale Analog Input ............................................................................................................... 20
Figure 8.Full-Scale Output ........................................................................................................................ 21
Figure 9.ATAPI Block Diagram (x = channel pair 1, 2, 3, 4) ..................................................................... 22
Figure 10.Clock Generation ...................................................................................................................... 23
Figure 11.Right-Justified Serial Audio Formats ......................................................................................... 27
Figure 12.I²S Serial Audio Formats ........................................................................................................... 28
Figure 13.Left-Justified Serial Audio Formats ........................................................................................... 28
Figure 14.One Line Mode #1 Serial Audio Format .................................................................................... 29
Figure 15.One Line Mode #2 Serial Audio Format .................................................................................... 29
DS605F1
3
CIRRUS [ CIRRUS LOGIC ]
