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CS42426-CQZR 参数 Datasheet PDF下载

CS42426-CQZR图片预览
型号: CS42426-CQZR
PDF下载: 下载PDF文件 查看货源
内容描述: 114分贝192千赫6声道编解码器PLL [114 dB, 192 kHz 6-Ch Codec with PLL]
分类和应用: 解码器编解码器消费电路商用集成电路
文件页数/大小: 73 页 / 1381 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS42426  
6.4.2 ADC FUNCTIONAL MODE (ADC_FMX)  
Default = 00  
00 - Single-Speed Mode (4 to 50 kHz sample rates)  
01 - Double-Speed Mode (50 to 100 kHz sample rates)  
10 - Quad-Speed Mode (100 to 192 kHz sample rates)  
11 - Reserved  
Function:  
Selects the required range of sample rates for the ADC serial port (ADC_SP). These bits must be set  
to the corresponding sample rate range when the ADC_SP is in Master or Slave Mode.  
6.4.3 ADC CLOCK SOURCE SELECT (ADC_CLK SEL)  
Default = 0  
0 - ADC_SDOUT clocked from the DAC_SP.  
1 - ADC_SDOUT clocked from the ADC_SP.  
Function:  
Selects the desired clocks for the ADC serial output.  
6.4.4 DAC DE-EMPHASIS CONTROL (DAC_DEM)  
Default = 0  
Function:  
Enables the digital filter to maintain the standard 15µs/50µs digital de-emphasis filter response at the  
auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless  
of this register setting, at any other sample rate. If the FRC_PLL_LK bit is set to a ‘1’b, the auto-detect  
sample rate feature is disabled. To apply the correct de-emphasis filter, use the DE-EMPH bits in the  
Interrupt Control (address 1Eh) register to set the appropriate sample rate.  
DAC_DEM FRC_PLL_LK  
DE-EMPH[1:0]  
reg1Eh[5:4]  
De-Emphasis  
Mode  
reg03h[1]  
reg06h[0]  
0
1
1
X
0
1
XX  
XX  
00  
01  
10  
11  
No De-Emphasis  
Auto-Detect Fs  
Reserved  
32 kHz  
44.1 kHz  
48 kHz  
Table 5. DAC De-Emphasis  
44  
DS604F1