CS42426
+3.3
V to +5 V
+5
V
0.01 µF 0.1 µF
0.01 µF 0.1 µF
0.1 µF
0.1 µF
0.01 µF
0.01 µF
+
+
+
+
10 µF
10 µF
10 µF
10 µF
4
51
V D
41
24
V A
V A
V D
36
2
A nalog O utput Buffer
and
A O U TA1+
A O U TA 1-
37
48
47
46
45
44
43
42
M ute C ircuit (optional)
G P O 1
G P O 2
G P O 3
G P O 4
G P O 5
G P O 6
G P O 7
35
34
2
A O U TB1+
A O U TB 1-
A nalog O utput B uffer
and
M ute Circuit (optional)
32
33
2
A O U TA2+
A O U TA 2-
A nalog O utput B uffer
and
M ute C ircuit (optional)
31
30
2
+1.8
to +5.0
V
53
A O U TB2+
A O U TB 2-
A nalog O utput B uffer
V LS
V
and
0.1 µF
M ute Circuit (optional)
59
O M C K
28
29
2
A O U TA3+
A O U TA 3-
A nalog O utput B uffer
58
57
and
A D CIN 1
A D CIN 2
M ute Circuit (optional)
27
26
2
A O U TB3+
A O U TB 3-
A nalog O utput B uffer
and
M ute Circuit (optional)
55
56
60
61
R M C K
CS42426
A DC _S D O U T
A D C _LR C K
A DC _S C LK
+V A
M ute
D rive
(optional)
*
*
38
D V D
P rocessor
M U TE C
3
2
1
*
P ull up or dow n as
DA C _LR C K
D AC _S C LK
DA C _S D IN1
27 M Hz
required on startup if the
M ute C ontrol is used.
15
16
14
13
A nalog
A INL+
A INL-
A INR +
A IN R -
2700 pF*
64
63
Input
B uffer
Left A nalog Input
D A C _S D IN 2
DA C _S D IN3
1
A nalog
11
12
7
IN T
2I7n0p0utpF*
Right Analog Input
1
B uffer
RS T
S C L/C C LK
S D A/C D O UT
8
9
A D1/CD IN
A D0/CS
10
17
18
V Q
**
2
**
+
FILT+
+
2
kΩ
kΩ
4.7 µF
0.1 µF
0.1 µF
100 µF
6
19
39
RE FG N D
LP FLT
V LC
0.1 µF
3
R FILT
** R esistors are required for
I2
control port operation
A G N D
25
A G N D
40
D G N D D G ND
C
3
3
C FILT
C RIP
5
52
C onnect D G N D and A G N D at single point near C odec
1. S ee the A D C Input Filter section in the A ppendix.
2. S ee the D A C O utput Filter section in the A ppendix.
3. S ee the P LL Filter section in the Appendix.
Figure 6. Typical Connection Diagram using the PLL
DS604F1
19
CIRRUS [ CIRRUS LOGIC ]
