CS42428
3.2.2 External Input Filter
The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter
will reject signals within the stopband of the filter. However, there is no rejection for input signals which
are (n × 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the CDB42418 for a rec-
ommended analog input buffer that will attenuate any noise energy at 6.144 MHz, in addition to providing
the optimum source impedance for the modulators. The use of capacitors which have a large voltage coef-
ficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity.
3.2.3 High Pass Filter and DC Offset Calibration
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. The high pass filter can be independently enabled and disabled. If the HPF_Freeze bit is set during
normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC
offset will continue to be subtracted from the conversion result. This feature makes it possible to perform
a system DC offset calibration by:
1) Running the CS42428 with the high pass filter enabled until the filter settles. See the Digital Filter
Characteristics for filter settling time.
2) Disabling the high pass filter and freezing the stored DC offset.
The high pass filters are controlled using the HPF_FREEZE bit in the register “Misc Control (address
05h)” on page 36.
3.3
Analog Outputs
3.3.1 Line Level Outputs and Filtering
The CS42428 contains on-chip buffer amplifiers capable of producing line level differential outputs. These
amplifiers are biased to a quiescent DC level of approximately VQ.
The delta-sigma conversion process produces high frequency noise beyond the audio passband, most of
which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using
an off-chip low pass filter. The recommended output filter configuration is shown in the CDB42418. This
filter configuration accounts for the normally differing AC loads on the AOUT+ and AOUT- differential
output pins. It also shows an AC coupling configuration which minimizes the number of required AC cou-
pling capacitors.
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