CS42418
4.5.4
One-Line Mode (OLM) Configurations
4.5.4.1 OLM Config #1
One-Line Mode Configuration #1 can support up to 8 channels of DAC data, and 6 channels of ADC data.
This is the only configuration which will support up to 24-bit samples at a sampling frequency of 48 kHz on
all channels for both the DAC and ADC.
Register / Bit Settings
Description
Functional Mode Register (addr = 03h)
Set DAC_FMx = ADC_FMx = 00,01,10
Set ADC_CLK_SEL = 0
DAC_LRCK must equal ADC_LRCK; sample rate conversion not supported
Configure ADC_SDOUT to be clocked from the DAC_SP clocks.
Interface Format Register (addr = 04h)
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01,10
Select the digital interface format when not in One-Line Mode
Select ADC operating mode, see table below for valid combinations
Select DAC operating mode, see table below for valid combinations
Set DAC_OLx bits = 00,01,10
Misc. Control Register (addr = 05h)
Set DAC_SP M/S = 1
Configure DAC Serial Port to Master Mode.
Configure ADC Serial Port to Master Mode.
Set ADC_SP M/S = 1
Identify external ADC clock source as SAI Serial Port.
Set EXT ADC SCLK = 0
DAC Mode
Not One-Line Mode
DAC_SCLK=64Fs
Not One- DAC_LRCK=SSM/DSM/QSM DAC_LRCK=SSM/DSM
One-Line Mode #1
One-Line Mode #2
DAC_SCLK=128Fs
not valid
Line Mode
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
DAC_SCLK=128Fs
DAC_SCLK=128Fs
One-Line DAC_LRCK=SSM/DSM
Mode #1 ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
ADC Mode
not valid
DAC_SCLK=256Fs
One-Line DAC_LRCK=SSM
Mode #2 ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
not valid
MCLK
64Fs
LRCK
SCLK
ADC_SCLK
ADC_LRCK
MCLK
SDOUT1
SDOUT2
RMCK
64Fs,128Fs, 256Fs
ADCIN1
ADCIN2
DAC_SCLK
SCLK_PORT1
DAC_LRCK
LRCK_PORT1
SDIN_PORT1
ADC Data
ADC_SDOUT
CS5361
CS5361
SCLK_PORT2
LRCK_PORT2
DAC_SDIN1
DAC_SDIN2
SDOUT1_PORT2
SDOUT2_PORT2
SDOUT3_PORT2
SDOUT4_PORT2
DAC_SDIN3
DAC_SDIN4
DIGITAL AUDIO
PROCESSOR
CS42418
Figure 17. OLM Configuration #1
DS603F1
31
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