CS42416-CQZR 参数 Datasheet PDF下载

型号：	CS42416-CQZR
PDF下载：	下载PDF文件查看货源
内容描述：	110分贝192千赫6声道编解码器PLL [110 dB, 192 kHz 6-Ch Codec with PLL]
分类和应用：	解码器编解码器消费电路商用集成电路
文件页数/大小：	73 页 / 1386 K
品牌：	CIRRUS [ CIRRUS LOGIC ]

CS42416

LIST OF TABLES

Table 1. Common OMCK Clock Frequencies............................................................................................ 24

Table 2. Common PLL Output Clock Frequencies..................................................................................... 24

Table 3. Slave Mode Clock Ratios............................................................................................................. 25

Table 4. Serial Audio Port Channel Allocations ......................................................................................... 26

Table 5. DAC De-Emphasis....................................................................................................................... 44

Table 6. Digital Interface Formats.............................................................................................................. 45

Table 7. ADC One-Line Mode.................................................................................................................... 45

Table 8. DAC One-Line Mode.................................................................................................................... 45

Table 9. RMCK Divider Settings ................................................................................................................ 48

Table 10. OMCK Frequency Settings ........................................................................................................ 48

Table 11. Master Clock Source Select....................................................................................................... 49

Table 12. PLL Clock Frequency Detection................................................................................................. 50

Table 13. Example Digital Volume Settings............................................................................................... 53

Table 14. ATAPI Decode ........................................................................................................................... 54

Table 15. Example ADC Input Gain Settings............................................................................................. 55

Table 16. PLL External Component Values............................................................................................... 62

DS602F1