CS42416
SWITCHING CHARACTERISTICS
(For CQZ, T = -10 to +70° C; For DQZ, T = -40 to +85° C;
A
A
VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C = 30 pF)
L
Parameters
RST Pin Low Pulse Width
Symbol
Min
1
Typ
-
Max
-
Units
ms
(Note 12)
30
-
200
-
kHz
ps RMS
%
PLL Clock Recovery Sample Rate Range
RMCK Output Jitter
-
200
50
-
(Note 14)
(Note 15)
(Note 13)
(Note 13)
45
55
RMCK Output Duty Cycle
OMCK Frequency
1.024
40
25.600
60
MHz
%
50
50
50
OMCK Duty Cycle
45
55
%
DAC_SCLK, ADC_SCLK Duty Cycle
DAC_LRCK, ADC_LRCK Duty Cycle
Master Mode
45
55
%
tsmd
tlmd
0
0
-
-
15
15
ns
ns
RMCK to DAC_SCLK, ADC_SCLK active edge delay
RMCK to DAC_LRCK, ADC_LRCK delay
Slave Mode
DAC_SCLK, ADC_SCLK Falling Edge to ADC_SDOUT,
ADC_SDOUT Output Valid
tdpd
-
(Note 16)
ns
tlrpd
tds
-
-
-
-
-
26.5
ns
ns
ns
ns
ns
DAC_LRCK, ADC_LRCK Edge to MSB Valid
DAC_SDIN Setup Time Before DAC_SCLK Rising Edge
DAC_SDIN Hold Time After DAC_SCLK Rising Edge
DAC_SCLK, ADC_SCLK High Time
10
30
20
20
-
-
-
-
tdh
tsckh
tsckl
DAC_SCLK, ADC_SCLK Low Time
DAC_SCLK, ADC_SCLK falling to DAC_LRCK, SAI_LRCK
Edge
tlrck
-25
-
+25
ns
Notes:
12. After powering-up the CS42416, RST should be held low after the power supplies and clocks are set-
tled.
13. See Table 1 on page 24 for suggested OMCK frequencies
14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 48 is set to Multiply by 2.
16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode.
DAC_LRCK
ADC_LRCK
(input)
DAC_SCLK
ADC_SCLK
(output)
t
t
t
sckh
t
lrckd
lrcks
sckl
DAC_SCLK
ADC_SCLK
(input)
DAC_LRCK
ADC_LRCK
(output)
t
DAC_SDINx
smd
t
lmd
t
lrpd
t
t
t
ds
dh
dpd
ADC_SDOUT
RMCK
MSB
MSB-1
Figure 1. Serial Audio Port Master Mode Timing
Figure 2. Serial Audio Port Slave Mode Timing
DS602F1
11
CIRRUS [ CIRRUS LOGIC ]
