CS42406
SWITCHING CHARACTERISTICS - DAC SERIAL AUDIO PORT (Logic “0” = GND =
0 V, Logic “1” = VLS)
Parameter
Symbol
Min
Typ
Max
Unit
MCLK Specifications
MCLK Frequency
1.024
22
-
-
-
12.8
25.6
55
MHz
MHz
%
MCLK Duty Cycle
45
Single-Speed*
DAC_LRCK Duty Cycle
45
-
-
-
-
-
55
%
Hz
ns
ns
ns
ns
ns
ns
DAC_SCLK Frequency
128×Fs
DAC_SCLK Pulse Width Low
t
20
20
20
20
20
20
-
sclkl
DAC_SCLK Pulse Width High
t
sclkh
-
DAC_SCLK rising to DAC_LRCK edge delay
DAC_SCLK rising to DAC_LRCK edge setup time
SDINx valid to DAC_SCLK rising setup time
DAC_SCLK rising to SDINx hold time
Double-Speed*
t
slrd
t
slrs
t
sdlrs
t
sdh
DAC_LRCK Duty Cycle
45
-
-
-
-
-
55
%
Hz
ns
ns
ns
ns
ns
ns
DAC_SCLK Frequency
64×Fs
DAC_SCLK Pulse Width Low
t
20
20
20
20
20
20
-
sclkl
DAC_SCLK Pulse Width High
t
sclkh
-
DAC_SCLK rising to DAC_LRCK edge delay
DAC_SCLK rising to DAC_LRCK edge setup time
SDINx valid to DAC_SCLK rising setup time
DAC_SCLK rising to SDINx hold time
Quad-Speed*
t
slrd
t
slrs
t
sdlrs
t
sdh
DAC_LRCK Duty Cycle
45
-
-
-
-
-
55
%
Hz
ns
ns
ns
ns
ns
ns
DAC_SCLK Frequency
MCLK/2
DAC_SCLK Pulse Width Low
t
20
20
20
20
20
20
-
-
sclkl
DAC_SCLK Pulse Width High
t
sclkh
DAC_SCLK rising to DAC_LRCK edge delay
DAC_SCLK rising to DAC_LRCK edge setup time
SDINx valid to DAC_SCLK rising setup time
DAC_SCLK rising to SDINx hold time
t
slrd
t
slrs
t
sdlrs
t
sdh
* For a description of Speed Modes, please refer to Section 4.1.2 on page 30.
21
CIRRUS [ CIRRUS LOGIC ]
