CS42406
6. REGISTER DESCRIPTIONS
Note: All registers are read/write in I²C mode and write only in SPI, unless otherwise stated.
6.1
MODE CONTROL 1 (ADDRESS 01H)
7
AMUTE
1
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
DEM1
0
2
DEM0
0
1
FM1
0
0
FM0
0
6.1.1 AUTO-MUTE (AMUTE) BIT 7
Default = 1
0 - Disabled
1 - Enabled
Function:
The CS42406 DAC output will mute following the reception of 8192 consecutive audio samples of
static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done
independently for each channel. The quiescent voltage on the output will be retained and the Mute
Control pin will go active during the mute period. The muting function is affected, similar to volume
control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.
6.1.2 DIGITAL INTERFACE FORMAT (DIF) BIT 6-4
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
Function:
The required relationship between the DAC_LRCK, DAC_SCLK, and SDINx is defined by the Digital
Interface Format and the options are detailed in Figures 28-30.
DIF2
DIF1
DIF0
DESCRIPTION
Left Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
Format
FIGURE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
-
28
29
30
30
30
30
-
-
-
Reserved
Table 7. Digital Interface Formats - Control Port Mode
44
DS614PP2
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