CS4235
CrystalClear Low Cost ISA Audio System
TM
TIMING PARAMETERS
(Continued)
Parameter
Symbol
Min
Max
Units
Parallel Bus Timing
IOW or IOR strobe width
Data valid to IOW rising edge
IOR falling edge to data valid (read cycle)
SA <> and AEN setup to IOR or IOW falling edge
SA <> and AEN hold from IOW or IOR rising edge
DACK<> inactive to IOW or IOR falling edge (DMA cycle
immediately followed by a non-DMA cycle)
(Note 8)
DACK<> active from IOW or IOR rising edge (non-DMA
cycle completion followed by DMA cycle)
(Note 8)
DACK<> setup to IOR falling edge (DMA cycles)
DACK<> setup to IOW falling edge
Data hold from IOW rising edge
DRQ<> hold from IOW or IOR falling edge
(assumes no more DMA cycles needed)
DTM(I10) = 0
DTM(I10) = 1
(Note 8)
(write cycle)
t
STW
t
WDSU
t
RDDV
t
ADSU
t
ADHD
t
SUDK1
t
SUDK2
t
DKSUa
t
DKSUb
t
DHD2
t
DRHD
t
BWDN
t
DHD1
t
DKHDa
t
DKHDb
(Note 1) t
RESDRV
(Note 1, 9)
(Notes 1, 11)
(Notes 1, 11)
(Notes 1, 11)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Fs
t
PD1
t
PD2
t
S1
t
H1
t
INIT
(Note 1, 10) t
EEPROM
90
22
-
22
10
60
0
25
25
15
-
-25
80
0
25
25
1
3
1
16.92
24
24
3.918
-
-20
30
30
-
-
60
-
-
-
-
-
-
-
45
-
-
25
-
-
-
10
190
16.95
-
-
50
60
20
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
MHz
ns
ns
kHz
ns
ns
ns
ns
Time between rising edge of IOW or IOR to next falling
edge of IOW or IOR
Data hold from IOR rising edge
DACK<> hold from IOW rising edge
DACK<> hold from IOR rising edge
RESDRV pulse width high
Initialization Time
EEPROM Read Time
XTAL, 16.9344 MHz, frequency
XTALI high time
XTALI low time
Sample Frequency
CS4610 DSP Serial Port Timing
SCLK rising to SDOUT valid
SCLK rising to FSYNC transition
SDIN valid to SCLK falling
SDIN hold after SCLK falling
Notes: 8. AEN must be high during DMA cycles.
9. Initialization time depends on the power supply circuitry, as well as the the type of clock used.
10. EEPROM read time is dependent on amount of data in EEPROM. Minimum time relates to no
EEPROM present. Maximum time relates to EEPROM data size of 1k bytes.
11. The Sample frequency specification must not be exceeded.
8
DS252PP2
CIRRUS [ CIRRUS LOGIC ]
