CS4226
SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: logic 0 = DGND, logic 1 =
VD+, C = 30 pF)
L
Parameter
Symbol
Min
Max
Units
2
®
2
I C Mode (SPI/I C = 1)
SCL Clock Frequency
f
-
100
kHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
scl
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
t
4.7
4.0
4.7
4.0
4.7
0
buf
t
hdst
t
low
high
sust
Clock High Time
t
t
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
(Note 14)
t
hdd
t
250
sud
t
1
r
t
300
f
t
4.7
susp
Notes: 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL
S/PDIF RECEIVER CHARACTERISTICS (RX1, RX2, RX3, RX4 pins only)
Parameter
Symbol
Min
Typ
10
-
Max
Units
kΩ
mVpp
mV
Input Resistance
Input Voltage
Z
-
-
-
N
V
200
-
TH
Input Hysteresis
Input Sample Frequency
CLKOUT Jitter
V
50
-
-
HYST
F
30
-
50
-
kHz
S
(Note 15)
(Note 16)
200
50
ps RMS
%
CLKOUT Duty Cycle (high time/cycle time)
40
60
Notes: 15. CLKOUT Jitter is for 256×FS selected as output frequency measured from falling edge to falling edge.
Jitter is greater for 384×Fs and 512×Fs as selected output frequency.
16. For CLKOUT frequency equal to 1×Fs, 384×Fs, and 512×Fs. See Master Clock Output section.
DIGITAL CHARACTERISTICS
Parameter
Symbol
Min
2.8
Typ
Max
Units
High-level Input Voltage
Low-level Input Voltage
(except RX1)
(except RX1)
V
-
-
-
(VD+)+0.3
V
V
V
IH
V
-0.3
0.8
-
IL
High-level Output Voltage at I = -2.0 mA
V
(VD+)-1.0
0
OH
Low-level Output Voltage at I = 2.0 mA
V
-
-
0.4
V
0
OL
Input Leakage Current
(Digital Inputs)
-
-
-
-
10
10
µA
µA
Output Leakage Current
(High-Impedance Digital Outputs)
DS188F4
9
CIRRUS [ CIRRUS LOGIC ]
