CS4226
3 REGISTER DESCRIPTION
3.1 Memory Address Pointer (MAP)
B7
B6
B5
B4
B3
B2
B1
B0
INCR
0
0
MAP4
MAP3
MAP2
MAP1
MAP0
MAP4-MAP0
INCR
Register Pointer
Auto Increment Control Bit
0 - No auto increment
1 - Auto increment on
This register defaults to 01h.
3.2
Reserved Byte (00h)
This byte is reserved for internal use and must be set to 00h for normal operation.
This register defaults to 00h.
3.3
Clock Mode Byte (01h)
B7
0
B6
CO1
B5
CO0
B4
CI1
B3
CI0
B2
CS2
B1
CS1
B0
CS0
CS2-CS0
Sets the source of the master clock.
0 - Crystal Oscillator or XTI at high frequency (PLL disabled)
1 - PLL driven by LRCKAUX at 1 Fs
2 - PLL driven by LRCK at 1 Fs
3 - PLL driven by XTI at 1 Fs
4 - PLL driven by RX1 data. This changes AUX port to S/PDIF port.
5 - PLL driven by RX2 data. This changes AUX port to S/PDIF port.
6 - PLL driven by RX3 data. This changes AUX port to S/PDIF port.
7 - PLL driven by RX4 data. This changes AUX port to S/PDIF port.
CI1-CI0
Determines frequency of XTI when PLL is disabled (not used if CS ≠ 0)
0 - 256 Fs
1 - 384 Fs
2 - 512 Fs
3 - not used
CO1-CO0
Sets CLKOUT frequency
0 - 256 Fs
1 - 384 Fs
2 - 512 Fs
3 - 1 Fs
This register defaults to 01h.
NOTE: If the sample rate on an input pin changes while using the PLL with RX1, RX2, RX3 or RX4,
the PLL will not resynchronize to the new sample rate. You must either change input pins or change
the Clock Mode Byte to something else and then change it back to the correct value. This will cause
the PLL to resync.
24
DS188F4
CIRRUS [ CIRRUS LOGIC ]
