CS4226
The first four bytes of the Channel Status block CS4226 S/PDIF receiver has the capability to
for both channel A and B can be accessed in automatically detect whether the incoming
the Receiver Channel Status Bytes. When the
CV bit is high, these bytes are being updated
and may be invalid. Additionally, the au-
data is a compressed AC-3/MPEG input. This
is accomplished by looking for an AC-3/MPEG
96-bit sync code consisting of six 16-bit words.
dio/non-audio, AC-3/MPEG data stream indi- The 96-bit sync code consists of: 0x0000,
cator and sampling frequency channel status 0x0000, 0x0000, 0x0000, 0xF872, and
bits may be output to pins 9, 10, 11 and 12, re-
spectively, see Table 5. This is accomplished
by setting the CSP bit to 1 in the Auxiliary Sta-
0x4E1F. When the sync code is detected, the
AUTODATA indicator (pin 10) will go high. If
no additional sync codes are detected within
tus Output Byte. The FREQ0/1 channel status the next 4096 frames, the AUTODATA indica-
bit outputs are decoded from the sampling fre- tor pin will return low until another sync code is
quency channel status bits after first referenc-
ing channel status byte 0, bit 0 (PRO or
consumer bit) which indicates the appropriate
location of these bits in the channel status data
stream.
detected.
2.6 Control Port Signals
The control port is used to load all the internal
settings. The operation of the control port may
be completely asynchronous with the audio
sample rate. However, to avoid potential inter-
ference problems, the control port pins should
remain static if no operation is required.
The received user bit is output on the
HOLD/RUBIT pin if the HPC bit in the AUX
Port Control Byte is set to 1. It can be sampled
with the rising or falling edge of LRCK if the au-
dio DSP port is in Master Mode.
2
The control port has 2 modes: SPI and I C,
with the CS4226 as a slave device. The SPI
mode is selected by setting the I C/SPI pin
low, and I C is selected by setting the I C/SPI
pin high. The state of this pin is continuously
monitored.
2
AUDIO
Pin 9
0 - Audio data
2
2
1 - Non-audio data
AUTODATA Pin 10
0 - No preamble detected in
last 4096 frames
1 - Preamble detected
FREQ0/1
Pin 11/12 00 - 44.1 kHz
2.6.1 SPI Mode
01 - 48 kHz
10 - Reserved
11 - 32 kHz
In SPI mode, CS is the CS4226 chip select sig-
nal, CCLK is the control port bit clock, (input
into the CS4226 from the microcontroller),
CDIN is the input data line from the microcon-
troller, CDOUT is the output data line to the mi-
crocontroller, and the chip address is
0010000. Data is clocked in on the rising edge
of CCLK and out on the falling edge.
Table 5. S/PDIF Receiver Status Outputs
2.5.6 AC-3/MPEG Auto Detection
For AC-3/MPEG applications, it is important to
know whether the incoming S/PDIF data
stream is digital audio or compressed
AC-3/MPEG data. This information is typically
conveyed by setting channel status bit 1
(audio/non-audio bit), but some AC-3/MPEG
sources may not strictly adhere to this conven-
tion and the bit may not be properly set. The
Figure 7 shows the control port timing in SPI
mode. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address, and
they must be 0010000. The eighth bit is a
read/write indicator (R/W), which should be
18
DS188F4
CIRRUS [ CIRRUS LOGIC ]
