CS4226
SWITCHING CHARACTERISTICS
Parameter
Audio ADC's & DAC's Sample Rate
XTI Frequency
XTI Pulse Width High
(XTI = 256, 384, or 512 Fs)
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
RX, XTI, LRCK, LRCKAUX
(Note 11)
(DSCK = 0)
t
dpd
t
lrpd
(DSCK=0)
(DSCK=0)
t
ds
t
dh
t
sck
(DSCK=0)
t
mslr
(Outputs loaded with 30 pF)
Symbol
Fs
Min
4
1.024
10
21
31
10
21
31
30
-
500
-
-
-
-
1 -
-------------------
(
256
)Fs
Typ
-
-
-
-
-
-
-
-
-
500
-
-
-
-
-
-
±10
50
-
-
-
-
-
Max
50
26
-
-
-
-
-
-
50
-
-
1 -
------------------- + 20
(
384
)Fs
Units
kHz
MHz
ns
ns
ns
ns
ns
ns
kHz
ps
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
XTI Pulse Width Low
PLL Clock Recovery Frequency
XTI Jitter Tolerance
PDN Low Time
SCLK Falling Edge to SDOUT Output Valid
LRCK edge to MSB valid
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
40
25
25
-
-
-
-
-
-
-
-
Master Mode
SCLK Period
SCLK Falling to LRCK Edge
SCLK Duty Cycle
-
-
Slave Mode
SCLK Period
SCLK High Time
SCLK Low Time
SCLK Rising to LRCK Edge
LRCK Edge to SCLK Rising
(DSCK=0)
(DSCK=0)
t
sckw
t
sckh
t
sckl
t
lrckd
t
lrcks
1
-------------------
-
(
128
)Fs
40
40
20
40
Notes: 11. After powering up the CS4226, PDN should be held low until the power supply is settled.
LRCK
LRCKAUX
(input)
t
sck
SCLK*
SCLKAUX*
(output)
t
mslr
LRCK
LRCKAUX
(output)
t lrckd
t
lrcks
t
sckh
t sckl
SCLK*
SCLKAUX*
(input)
SDIN1
SDIN2
SDIN3
DATAUX
t sckw
t
lrpd
t ds
t dh
MSB
t dpd
MSB-1
SDOUT1
SDOUT2
SDOUT1
SDOUT2
*SCLK, SCLKAUX shown for DSCK = 0 and ASCK = 0.
SCLK & SCLKAUX inverted for DSCK = 1 and ASCK = 1, respectively.
Audio Ports Master Mode Timing
Audio Ports Slave Mode and Data I/O timing
DS188F4
7
CIRRUS [ CIRRUS LOGIC ]
