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CS4222-BS 参数 Datasheet PDF下载

CS4222-BS图片预览
型号: CS4222-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 20位立体声音频编解码器与音量控制 [20-Bit Stereo Audio Codec with Volume Control]
分类和应用: 解码器编解码器消费电路商用集成电路光电二极管
文件页数/大小: 29 页 / 616 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4222  
4.6.2 I2C Mode  
2
In I C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with  
the clock-to-data relationship as shown in Figure 12. There is no CS pin. Pin AD0 forms the partial chip ad-  
dress and should be tied to VD or DGND as desired. The upper 6 bits of the 7 bit address field must be  
001000. In order to communicate with the CS4222, the LSB of the chip address field (first byte sent to the  
CS4222) should match the setting of the AD0 pin. The eighth bit of the address byte is the R/W bit (high for  
a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer which selects  
the register to be read or written. If the operation is a read, the contents of the register pointed to by the  
Memory Address Pointer will be output. Setting the auto increment bit in MAP allows successive reads or  
writes of consecutive registers. Each byte is separated by an acknowledge bit.  
ADDR  
AD0  
001000  
R/W  
ACK  
DATA 1-8  
ACK  
DATA 1-8  
ACK  
SDA  
SCL  
Start  
Stop  
2
Figure 12. Control Port Timing, I C mode  
4.6.3 Control Port Bit Definitions  
2
All registers can be written and read in I C mode, except the Converter Status Report Byte (#6) and the  
CLKE and CALP bits in the ADC control byte (#1) which are read only. SPI mode only allows for register  
writing (see the following bit definition tables for bit assignment information).  
4.7 De-Emphasis  
The CS4222 is capable of digital de-emphasis for 32, 44.1, or 48 kHz sample rates. Implementation of digital  
de-emphasis requires reconfiguration of the digital filter to maintain the filter response at multiple sample rates  
(see Figure 13).  
De-emphasis control is achieved with the DEM1/0 pins or through the DEM2-0 bits in the DSP Port Mode Byte  
(#2). The default state on power-up is de-emphasis controlled via the DEM1/0 pins (DEM2-0 bits=0). DEM1/0  
pin control is defined in Table 4.  
Gain  
dB  
Table 4. De-Emphasis filter control  
T1 = 50 µs  
0 dB  
DEM 1  
DEM 0  
De-emphasis  
32 kHz  
0
0
1
1
0
1
0
1
44.1 kHz  
48 kHz  
T2 = 15 µs  
Frequency  
-10 dB  
OFF  
F1  
F2  
Figure 13. De-emphasis Curve.  
22  
DS236F1