CS4222
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (SPI) (Inputs:
Logic 0 = DGND, Logic 1 = VD)
Parameter
Symbol
Min
Max
Unit
SPI Mode
CCLK Clock Frequency
f
-
6
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
sck
t
500
500
1.0
20
66
66
40
15
-
-
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
srs
t
-
(Note 8)
spi
csh
css
t
t
-
CS High Time Between Transmissions
-
CS Falling to CCLK Edge
CCLK Low Time
t
-
scl
sch
dsu
CCLK High Time
t
-
-
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
t
(Note 9)
(Note 10)
(Note 10)
t
-
dh
t
100
100
r2
t
-
f2
Notes: 8.
t
only needed before first falling edge of CS after RST rising edge. t = 0 at all other times.
spi spi
9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For f
< 1 MHz.
sclk
RST
t
t
srs
spi
CS
t
t
t
css
scl
sch
t
csh
CCLK
t
t
r2
f2
CDIN
t
t
dsu
dh
Figure 2. Control Port Timing - SPI Mode
10
DS236F1
CIRRUS [ CIRRUS LOGIC ]
