CS4227
SWITCHING CHARACTERISTICS
(T
A
= 25 °C; VA+, VD+ = +5 V ±5%; outputs loaded with 30 pF.)
Parameter
Audio ADC’s and DAC’s Sample Rate
XTI Frequency
XTI = 256, 384, or 512 Fs
XTI Pulse Width High
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
XTI Pulse Width Low
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
XTI Jitter Tolerance
CLKOUT Jitter
(Note 9)
CLKOUT Duty Cycle (high timer/cycle time)
(Note 10)
PDN Low Time
SCLK Falling Edge to SDOUT Output Valid
LRCK edge to MSB valid
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Master Mode
SCLK Falling to LRCK Edge
SCLK Period
SCLK Duty Cycle
Slave Mode
SCLK Period
SCLK High Time
SCLK Low Time
SCLK Rising to LRCK Edge
LRCK Edge to SCLK Rising
(Note 11)
DSCK = 0
DSCK = 0
DSCK = 0
DSCK = 0
(Note 14)
Symbol
Fs
Min
4
1.024
10
21
31
10
21
31
-
-
40
500
-
-
-
-
-
-
-
Note 13
40
40
20
40
Typ
-
-
-
-
-
-
-
-
500
200
50
-
-
-
-
-
±10
-
50
-
-
-
-
-
Max
50
26
-
-
-
-
-
-
-
-
60
-
Note 12
40
25
25
-
-
-
-
-
-
-
-
Unit
kHz
MHz
ns
ns
ps
psRMS
%
ns
ns
ns
ns
ns
ns
-
%
ns
ns
ns
ns
ns
t
dpd
t
lrpd
t
ds
t
dh
t
mslr
-
DSCK = 0
DSCK = 0
t
sckw
t
sckh
t
sckl
t
lrckd
t
lrcks
Notes: 9. CLKOUT Jitter is for 256x Fs selected as output frequency measured from falling edge to falling edge.
Jitter is greater for 384x Fs and 512x Fs as selected output frequency.
10. For CLKOUT frequency equal to 1x Fs, 384x Fs, and 512x Fs. See Master Clock Output section.
11. After powering up the CS4227, PDN should be held low for 1 ms to allow the power supply to settle.
1
12. --------------------- + 20
(
384
)Fs
13.
14.
1
---------------------
(
128
)Fs
1
-------------------
(
256
)Fs
6
DS281PP2
CIRRUS [ CIRRUS LOGIC ]
