CS4225
SWITCHING CHARACTERISTICS (T = 25°C; VA+, VD+ = +5V, outputs loaded with 30pF)
A
Parameter
Symbol
Min
80
25
25
-
Typ
Max
Units
SCLK period
t
-
-
-
-
-
-
ns
sckw
SCLK high time
t
ns
sckh
SCLK low time
t
-
ns
sckl
Input Transition Time
Input Clock Frequency
10% to 90% points
10
ns
Crystals
XTI
32
32
-
-
26000
26000
kHz
kHz
Input Clock (XTI) low time
Input Clock (XTI) high time
Input clock jitter tolerance
PLL clock recovery frequency
30
30
-
-
-
-
-
-
ns
ns
ps
500
LRCK, LRCKAUX
SCLK, SCLKAUX
32
2.048
-
-
50
3.200
kHz
MHz
CLKOUT duty cycle
45
4
50
-
55
50
-
%
kHz
ns
ns
ns
ns
ns
ns
ns
ns
Audio ADC’s & DAC’s sample rate
RST-PDN low time
Fs
(Note 5)
500
-
-
MSB output from LRCK edge (Format 1 and 3)
SDOUT output from SCLK edge
t
-
50
50
35
35
-
lrpd
dpd
t
-
-
SDIN setup time before SCLK edge
SDIN hold time after SCLK edge
t
-
-
ds
t
-
-
dh
LRCK to SCLK delay (slave mode)
LRCK to SCLK setup (slave mode)
LRCK to SCLK alignment (master mode)
t
35
35
-20
-
lrckd
t
-
-
lrcks
t
-
20
mslr
Note: 5. After Powering up the CS4225, RST-PDN should be held low for 50 ms to allow the voltage
reference to settle.
LRCK
LRCKAUX
(input)
t
t
t
sckh
t
lrckd
lrcks
sckl
SCLK*
SCLKAUX*
(input)
SCLK*
SCLKAUX*
(output)
t
sckw
SDIN1
SDIN2
t
mslr
DATAUX
LRCK
LRCKAUX
(output)
t
t
t
lrpd
t
ds
dh
dpd
SDOUT1
SDOUT2
MSB
MSB-1
*Active edge of SCLK, SCLKAUX depends on selected format.
Audio Ports Master Mode Timing
Audio Ports Slave Mode and Data I/O timing
DS86PP8
5
CIRRUS [ CIRRUS LOGIC ]
