CS4225
56 pF
FUNCTIONAL DESCRIPTION
Overview
1.0 uF
10 k
20 k
1.0 uF
Line In
Right
_
AINxR
The CS4225 has 2 channels of 16-bit analog-to-
digital conversion and 4 channels of 16-bit
digital-to-analog conversion. An auxiliary 12-bit
ADC is also provided. The ADCs and the DACs
are delta-sigma type converters. The ADC inputs
have adjustable input gain, while the DAC out-
puts have adjustable output attenuation.
+
Example
Op-Amps
are
5 k
CMOUT
0.47 uF
0.47 uF
1.0 uF
MC34074
1.0 uF
+
_
Line In
Left
20 k
AINxL
10 k
Digital audio data for the DACs and from the
ADCs is communicated over a serial port. Sepa-
rate pins for input and output data are provided,
allowing concurrent writing to and reading from
the device. Control for the functions available on
the CS4225 are communicated over a serial mi-
crocontroller style interface, or may be set via
dedicated mode pins. Figure 1 shows the recom-
mended connection diagram for the CS4225.
Op-amps are run
from VA+ (+5V)
and AGND.
56 pF
Figure 2 - Optional Line Input Buffer
The input pair for the 16-bit ADCs is selected by
IS0 and IS1, which are accessible in the Input
Selection Byte in software mode or dedicated
pins in the hardware mode. Antialiasing filters
follow the input mux, providing antialiasing for
the input channels. These filters consist of inter-
nal resistors and external capacitors attached to
the CR and CL pins. The CR and CL capacitors
must be low voltage coefficient type, such as
NPO.
Analog Inputs
Line Level Inputs
AIN1R, AIN1L, AIN2R, AIN2L, AIN3R, AIN3L
and AINAUX are the line level input pins (See
Figure 1). These pins are internally biased to the
CMOUT voltage (nominally 2.1V). A 1µF DC
blocking capacitor allows signals centered
around 0V to be input. Figure 2 shows an op-
tional dual op amp buffer which combines level
shifting with a gain of 0.5 to attenuate the stand-
The analog signal is input to the 12-bit ADC via
the AINAUX pin. An antialiasing filter of 150Ω
with 0.01µF to ground is required (See Figure 1)
along with a series DC blocking capacitor. The
AINAUX signal is normally routed to the 12-bit
ADC. This signal may also be routed to the Left
16-bit ADC (replacing the selected left input),
under control of the AIM bit in the 12-bit ADC
Mode Byte. In this mode, the input antialiasing
filters and gain adjustment operates on the
AINAUX signal.
ard line level of 2V
to 1V . The CMOUT
rms
rms
reference level is used to bias the op amps to
approximately one half the supply voltage.
Series DC blocking capacitors eliminate the con-
tribution of signal offset to the A/D converters.
The CS4225 offset calibration scheme yields
minimum DC offset values assuming that the in-
puts are AC coupled (DC blocking capacitor
present). If a DC blocking capacitor is not used,
a greater DC offset will occur. This offset could
Adjustable Input Gain
The signals from the line inputs are routed to a
programmable gain circuit which provides up to
+
be as high as 70 codes, with no gain.
10
DS86PP8
CIRRUS [ CIRRUS LOGIC ]
