CS4225
SWITCHING CHARACTERISTICS - CONTROL PORT
Parameter
I
2
C
®
Mode
(H/S = floating)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Note 11
Note 10
fscl
tbuf
thdst
tlow
thigh
tsust
thdd
tsud
tr
tf
tsusp
Symbol
(T
A
= 25
o
C; VD+, VA+ = 5V±10%;Inputs: logic 0 = DGND, logic 1 = VD+, C
L
= 20pF)
Min
Max
Units
0
4.7
4.0
4.7
4.0
4.7
0
250
100
kHz
µs
µs
µs
µs
µs
µs
ns
1
300
4.7
µs
ns
µs
Notes: 10. Use of the I
2
C
®
bus interface requires a license from Philips.
I
2
C
®
is a registered trademark of Philips Semiconductors.
11. Data must be held for sufficient time to bridge the 300ns transition time of SCL.
Stop
SDA
t
buf
Start
Repeated
Start
Stop
t hdst
t high
t
hdst
tf
t
susp
SCL
t
low
t
hdd
t
sud
t
sust
tr
DS86PP8
7
CIRRUS [ CIRRUS LOGIC ]
