CS4223 CS4224
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4224)
(T
A
= 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; C
L
= 30 pF)
Parameter
Symbol
f
sck
(Note 11)
(Note 12)
t
srs
t
spi
t
csh
t
css
t
scl
t
sch
t
dsu
(Note 13)
(Note 14)
(Note 14)
t
dh
t
r2
t
f2
Min
-
41
500
1.0
20
66
66
40
15
-
-
Max
6
-
-
-
-
-
-
-
-
100
100
Unit
MHz
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
SPI Mode (SPI/I2C = 0)
CCLK Clock Frequency
RST rising edge to CS falling
CCLK edge to CS falling
CS High Time between transmissions
CS falling to CCLK edge
CCLK Low Time
CCLK High Time
CDIN to CCLK rising setup time
CCLK rising to DATA hold time
Rise time of CCLK and CDIN
Fall time of CCLK and CDIN
Notes: 11. Not tested but guaranteed by design.
12. t
spi
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F
SCK
< 1 MHz.
RST
t srs
CS
t spi
CCLK
t r2
CDIN
t f2
t css
t scl
t sch
t csh
t dsu
t dh
Figure 2. SPI Control Port Timing
8
DS290PP3
CIRRUS [ CIRRUS LOGIC ]
