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CS4207-DNZ 参数 Datasheet PDF下载

CS4207-DNZ图片预览
型号: CS4207-DNZ
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗, 4入/ 6出的HD音频编解码器与耳机放大器 [Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp]
分类和应用: 解码器编解码器消费电路商用集成电路放大器
文件页数/大小: 144 页 / 782 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4207
Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp
DIGITAL to ANALOG FEATURES
DAC1 (Headphone)
ANALOG to DIGITAL FEATURES
ADC1 & ADC2
101 dB Dynamic Range (A-wtd)
-89 dB THD+N
Integrated Negative-voltage Regulator
No DC-blocking Capacitor Required
50 mW Power/Channel into 16
Ω
110 dB Dynamic Range (A-wtd)
-94 dB THD+N
Differential Balanced or Single-ended
Headphone Amplifier - GND Centered
DAC2 & DAC3 (Line Outs)
105 dB Dynamic Range (A-wtd)
-88 dB THD+N
Differential Balanced or Single-ended
Inputs
Analog Programmable Gain Amplifier
(PGA) ±12 dB, 1.0 dB Steps, with Zero
Cross Transitions and Mute
Pre-amplifier with Selectable 0 dB, +10 dB,
+20 dB, and +30 dB Gain Settings
Programmable, Low-noise MIC Bias Level
MIC Inputs
Each DAC Supports 32 kHz to 192 kHz Sample
Rates Independently.
Digital Volume Control
Each ADC Supports 8 kHz to 96 kHz Sample
Rates Independently
Additional Digital Attenuation Control
+6.0 dB to -57.5 dB in 0.5 dB Steps
Zero Cross and/or Soft Ramp Transitions
Independent Support of D0 and D3 Power
States for Each DAC
Fast D3 to D0 Transition
-13.0 dB to -51.0 dB in 1.0 dB steps
Zero Cross and/or Soft Ramp Transitions
Digital Interface for Two Dual Digital Mic Inputs
Independent Support of D0 and D3 Power
Audio Playback in Less Than 50 ms
States for Each ADC
VD
(1.5 V to 1.8 V)
VA, VA_REF
(3.3 V to 5.0 V)
VA_HP
(3.3 V to 5.0 V)
Chrg
Pump
Buck
+VHP
Chrg
Pump
Invert
-VHP
Level Translator
Vol/Mute
HD
Audio
Interface
SRC &
Multibit
ΔΣ
Modulator
SRC &
Multibit
ΔΣ
Modulator
SRC &
Multibit
ΔΣ
Modulator
Digital
Filter &
SRC
Digital
Filter &
SRC
2-Chnl
DAC1
2-Chnl
DAC2
2-Chnl
DAC3
Headphone
Amp - GND
Centered
Line
Out
Line
Out
Left HP Out
Right HP Out
+Left Line Out
-
+
Right Line Out
-
+Left Line Out
-
+
Right Line Out
-
HD Audio
Bus
VL_HD
(1.5 V to 3.3 V)
GPIO
S/PDIF OUT 2
S/PDIF OUT 1
VL_IF
(3.3 V)
S/PDIF IN
D-Mic Clock
D-Mic In
Vol/Mute
GPIO
SPDIF
TX2
SPDIF
TX1
HD Bus
Fs
Vol/Mute
Level Translator
Vol/Boost/
Mute
2-Chnl
ADC1
PGA
+
- Line/Mic In L
Line/Mic In R
+
+
- Mic/Line In L
+Mic/Line In R
-
Mic Bias
SENSE_A
128Fs Clock
Multiplier
SPDIF
RX SRC
Vol/Boost/
Mute
2-Chnl
ADC2
PGA
MIC
Bias
SPDIF
RX
Jack
Sense
Copyright
Cirrus Logic, Inc. 2009
(All Rights Reserved)
APR '09
DS880F1