CS4205
5.10 Record Gain Register (Index 1Ch)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Mute
0
0
0
GL3
GL2
GL1
GL0
0
0
0
0
GR3 GR2 GR1 GR0
Mute
Record Gain Mute. Setting this bit mutes the input to the L/R ADCs.
GL[3:0]
Left ADC Gain. The GL[3:0] bits control the input gain on the left channel of the analog
source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB
gain adjustment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain. See Table 10 for
further details.
GR[3:0]
Default
Right ADC Gain. The GR[3:0] bits control the input gain on the right channel of the analog
source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB
gain adjustment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain. See Table 10 for
further details.
8000h. This value corresponds to 0 dB gain and Mute ‘set’.
Gx3 - Gx0 Gain Level
1111
…
+22.5 dB
…
0001
0000
+1.5 dB
0 dB
Table 10. Record Gain Values
5.11 Record Gain Mic Register (Index 1Eh)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Mute
0
0
0
0
0
0
0
0
0
0
0
GM3 GM2 GM1 GM0
Mute
Mic Record Gain Mute. When ‘set’, mutes the input to the microphone ADC.
GM[3:0]
Mic ADC gain. The GM[3:0] bits control the input gain on the microphone source. The gain is
applied after the input mux and before the ADC. Each step corresponds to 1.5 dB gain ad-
justment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain. See Table 10 for further
details.
Default
8000h. This value corresponds to 0 dB gain and Mute ‘set’.
DS489PP4
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CIRRUS [ CIRRUS LOGIC ]
