CS3301
DIGITAL CHARACTERISTICS
CS3301
Typ
Parameter
Digital Characteristics
Symbol
Min
Max
Unit
High Level Input Drive Voltage
Low Level Input Drive Voltage
Input Leakage Current
(Note 17)
(Note 17)
V
0.6*VD
-
-
VD
0.8
+10
-
V
V
IH
V
I
0.0
IL
-
-
-
-
+1
9
-
µA
pF
ns
ns
IN
Digital Input Capacitance
C
IN
Rise Times, Digital Inputs Except CLK
Fall Times, Digital Inputs Except CLK
Master Clock Specifications
Master Clock Frequency
t
t
100
100
RISE
FALL
-
(Note 18)
f
2.0
2.048
2.2
60
25
25
300
1
MHz
%
CLK
DTY
RISE
FALL
Master Clock Duty Cycle
f
40
-
-
-
-
-
-
Master Clock Rise Time
t
t
ns
Master Clock Fall Time
-
ns
Master Clock Jitter (In-Band or Aliased In-Band)
Master Clock Jitter (Out-of-Band)
JTR
-
ps
IB
JTR
-
ns
OB
Notes: 17. Device is intended to be driven with CMOS logic levels.
18. When CLK is tied to DGND, an internal oscillator provides a master clock at approximately 2 MHz. CLK
should be driven for synchronous system operation.
t
t
fall
rise
0.9 * VD
0.1 * VD
Figure 2. Digital Input Rise and Fall Times
Gain Selection
GAIN2
GAIN1
GAIN0
Input Selection
800 Ω termination
INA only
MUX1
MUX0
x1
x2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
x4
INB only
x8
INA + INB
x16
x32
x64
reserved
Table 1. Digital Selections for Gain and Input Mux Control
8
DS595F3
CIRRUS [ CIRRUS LOGIC ]
