CS3001
CS3002
The loop gain plot shown in Figure 18 illustrates gin. The separation between the pole and the zero
the unity gain configuration, and indicates how this
is governed by the closed loop gain. The zero (z )
1
is modified when using the amplifier in a higher occurs at the intersection of the –100 dB/decade
gain configuration with compensation. If it is con- and –80 dB/decade slopes. The point X in the fig-
figured for higher gain, for example, 60 dB, the ure should be at closed loop gain plus 20 dB gain
x–axis will move up by 60 dB (line B). Capacitor margin. The value for C2 = 1/(2π R1 P1). Setting
C2 adds a zero and a pole. The modified plot indi- the pole of the filter to P1 = 1 MHz works very well
cates the effects of introducing the pole and zero and is independent of gain. As the closed loop gain
due to capacitor C2. The pole can be located at any is changed, the zero location is also modified if R1
frequency higher than the hand-over frequency, the remains fixed. Capacitor C2 can be increased in
zero has to be at a frequency lower than the hand-
over frequency so as to provide adequate gain mar-
value to limit the amplifier’s rising noise above
2 kHz.
-100 dB/dec
z1
p1
-80 dB/dec
X
Margin
B
Desired Closed
Loop Gain
-20 dB/dec
30kHz
1MHz
3MHz
FREQUENCY
Figure 18. Loop Gain Plot: Unity Gain and with Pole-zero Compensation
DS490F9
11
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