CS2300-OTP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T
A
= -10°C to +70°C (Commercial Grade);
C
L
= 15 pF.
Parameters
Clock Input Frequency (Auto R-Mod Disabled)
Clock Input Frequency (Auto R-mod Enabled)
Symbol
f
CLK_IN
f
CLK_IN
Conditions
Auto R Modifier = 1
Auto R Modifier = 0.5
Auto R Modifier = 0.25
f
CLK_IN
< 175 kHz
f
CLK_IN
> 175 kHz
(Notes
3, 4)
(Note
4)
Measured at VD/2
20% to 80% of VD
80% to 20% of VD
(Note
5)
(Notes
5, 6)
(Notes
5, 7)
Min
50 Hz
4
72
168
140
10
20
50 Hz
6
48
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
50
1.7
1.7
35
50
150
100
1
Max
30
59
138
256
-
-
-
80
75
52
3.0
3.0
110
-
-
200
3
Units
MHz
kHz
kHz
kHz
ns
ns
ms
kHz
MHz
%
ns
ns
ps rms
ps rms
ps rms
UI
ms
Clock Input Pulse Width
Clock Skipping Timeout
Clock Skipping Input Frequency
PLL Clock Output Frequency
PLL Clock Output Duty Cycle
Clock Output Rise Time
Clock Output Fall Time
Period Jitter
Base Band Jitter (100 Hz to 40 kHz)
Wide Band JItter (100 Hz Corner)
PLL Lock Time - CLK_IN (Note
8)
pw
CLK_IN
t
CS
f
CLK_SKIP
f
CLK_OUT
t
OD
t
OR
t
OF
t
JIT
t
LC
f
CLK_IN
< 200 kHz
f
CLK_IN
> 200 kHz
Notes:
3. t
CS
represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-
cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of t
CS
.
4. Only valid in clock skipping mode; See
“CLK_IN Skipping Mode” on page 10
for more information.
5.
f
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11.
6. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
7. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
8. 1 UI (unit interval) corresponds to t
CLK_IN
or 1/f
CLK_IN
.
DS844PP1
7
CIRRUS [ CIRRUS LOGIC ]
