CS2300-OTP
Fractional-N Clock Multiplier with Internal LCO
Features
Clock Multiplier / Jitter Reduction
General Description
The CS2300-OTP is an extremely versatile system
clocking device that utilizes a programmable phase lock
loop. The CS2300-OTP is based on a hybrid analog-
digital PLL architecture comprised of a unique combina-
tion of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for generation of a low-jitter clock relative to an external
noisy synchronization clock with frequencies as low as
50 Hz. The CS2300-OTP has many configuration op-
tions which are set once prior to runtime. At runtime
there are three hardware configuration pins available for
mode and feature selection.
The CS2300-OTP is available in a 10-pin MSOP pack-
age in Commercial (-10°C to +70°C) grade. Customer
development kits are also available for custom device
prototyping, small production programming, and device
evaluation. Please see
for complete details.
–
Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery 50 Hz to 30 MHz Clock
Source
Internal LCO Reference Clock
Highly Accurate PLL Multiplication Factor
–
Maximum Error Less Than 1 PPM in High-
Resolution Mode
Configurable Hardware Control Pins
Configurable Auxiliary Output
No External Analog Loop-filter
Components
One-Time Programmability
–
–
–
Minimal Board Space Required
3.3 V
Frequency Reference
Hardware Control
Hardware Configuration
PLL Output
Lock Indicator
Auxiliary
Output
LCO
Fractional-N
Frequency Synthesizer
6 to 75 MHz
PLL Output
N
50 Hz to 30 MHz
Frequency Reference
Output to Input
Clock Ratio
Digital PLL & Fractional
N Logic
Copyright
Cirrus Logic, Inc. 2009
(All Rights Reserved)
AUG '09
DS844F1
CIRRUS [ CIRRUS LOGIC ]
