CS2300-CP
5.2.2
CLK_IN Skipping Mode
CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses
for up to 20 ms (t ) at a time (see “AC Electrical Characteristics” on page 7 for specifications). CLK_IN
CS
skipping mode can only be used when the CLK_IN frequency is below 80 kHz. The ClkSkipEn bit enables
this function.
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Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 2 LCO cycles (518 ms to
634 ms) after CLK_IN is removed (see Figure 7). This is true as long as CLK_IN does not glitch or have
an effective change in period as the clock source is removed, otherwise the PLL will interpret this as a
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change in frequency causing clock skipping and the 2 LCO cycle time-out to be bypassed and the PLL
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to immediately unlock. If the prior conditions are met while CLK_IN is removed and 2 LCO cycles pass,
the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock Out-
put” on page 19. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified
time listed in the “AC Electrical Characteristics” on page 7 after which lock will be acquired and the PLL
output will resume.
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2
LCO cycles
2
LCO cycles
Lock Time
Lock Time
CLK_IN
PLL_OUT
UNLOCK
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=0
ClkSkipEn=0 or 1
ClkOutUnl=1
= invalid clocks
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Figure 7. CLK_IN removed for > 2 LCO cycles
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If CLK_IN is removed and then reapplied within 2 LCO cycles but later than t , the ClkSkipEn bit will
CS
have no effect and the PLL output will continue until CLK_IN is re-applied (see Figure 8). Once CLK_IN
is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be
determined by the ClkOutUnl bit during this time.
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2
LCO cycles
2
LCO cycles
tCS
tCS
Lock Time
Lock Time
CLK_IN
PLL_OUT
UNLOCK
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=0
ClkSkipEn=0 or 1
ClkOutUnl=1
= invalid clocks
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Figure 8. CLK_IN removed for < 2 LCO cycles but > t
CS
If CLK_IN is removed and then re-applied within t , the ClkSkipEn bit determines whether PLL_OUT
CS
continues while the PLL re-acquires lock (see Figure 9). When ClkSkipEn is disabled and CLK_IN is re-
moved the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only
for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl bit during this
DS843PP1
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CIRRUS [ CIRRUS LOGIC ]
