CS2300-CP
8.7
Function Configuration 2 (Address 17h)
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
ClkOutUnl
LFRatioCfg
Reserved
Reserved
Reserved
8.7.1
8.7.2
8.8
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
ClkOutUnl
Clock Output Enable Status
0
Clock outputs are driven ‘low’ when PLL is unlocked.
1
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
“PLL Clock Output” on page 19
Application:
Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the 32-bit User Defined Ratio.
LFRatioCfg
Ratio Bit Encoding Interpretation
20.12 - High Multiplier.
0
1
12.20 - High Accuracy.
Application:
“User Defined Ratio (RUD)” on page 15
Function Configuration 3 (Address 1Eh)
7
6
5
4
3
2
1
0
Reserved
ClkIn_BW2
ClkIn_BW1
ClkIn_BW0
Reserved
Reserved
Reserved
Reserved
8.8.1
Clock Input Bandwidth (ClkIn_BW[2:0])
Sets the minimum loop bandwidth when locked to CLK_IN.
ClkIn_BW[2:0]
Minimum Loop Bandwidth
000
1 Hz
001
2 Hz
010
4 Hz
011
8 Hz
100
16 Hz
32 Hz
64 Hz
128 Hz
101
110
111
Application:
“Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 14
Note: In order to guarantee that a change in minimum bandwidth takes effect, these bits must be set
prior to acquiring lock (removing and re-applying CLK_IN can provide the unlock condition necessary to
initiate the setting change). In production systems these bits should be configured with the desired values
prior to setting the EnDevCfg bits; this guarantees that the setting takes effect prior to acquiring lock.
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DS843PP1
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