CS2200-CP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T
A
= -10°C to +70°C (Commercial Grade);
C
L
= 15 pF.
Parameters
Crystal Frequency
Fundamental Mode XTAL
Reference Clock Input Frequency
Symbol
f
XTAL
Conditions
RefClkDiv[1:0]
= 10
RefClkDiv[1:0]
= 01
RefClkDiv[1:0]
= 00
RefClkDiv[1:0]
= 10
RefClkDiv[1:0]
= 01
RefClkDiv[1:0]
= 00
Min
8
16
32
8
16
32
45
8
6
Typ
-
-
-
-
-
-
-
-
50
1.7
1.7
70
50
175
1
-
Max
14
28
50
14
28
56
55
14
75
55
3.0
3.0
-
-
-
3
±0.5
Units
MHz
MHz
MHz
MHz
MHz
MHz
%
MHz
MHz
%
ns
ns
ps rms
ps rms
ps rms
ms
ppm
f
REF_CLK
Reference Clock Input Duty Cycle
Internal System Clock Frequency
PLL Clock Output Frequency
PLL Clock Output Duty Cycle
Clock Output Rise Time
Clock Output Fall Time
Period Jitter
Base Band Jitter (100 Hz to 40 kHz)
Wide Band JItter (100 Hz Corner)
PLL Lock Time - REF_CLK
Output Frequency Synthesis Resolution (Note
7)
D
REF_CLK
f
SYS_CLK
f
CLK_OUT
t
OD
t
OR
t
OF
t
JIT
Measured at VD/2
20% to 80% of VD
80% to 20% of VD
(Note
4)
(Notes
4, 5)
(Notes
4, 6)
t
LR
f
err
f
REF_CLK
= 8 to 75 MHz
45
-
-
-
-
-
-
0
Notes:
4.
f
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points;
AuxOutSrc[1:0]
= 11.
5. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
6. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
7. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
DS759F1
7
CIRRUS [ CIRRUS LOGIC ]
