CS2200-CP
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; C = 20 pF.
L
Parameter
CCLK Clock Frequency
Symbol
fccllk
tspi
Min
-
Max
Unit
MHz
ns
6
CCLK Edge to CS Falling
(Note 9)
500
1.0
20
66
66
40
15
-
-
CS High Time Between Transmissions
CS Falling to CCLK Edge
tcsh
tcss
tscl
-
µs
-
ns
CCLK Low Time
-
ns
CCLK High Time
tsch
tdsu
tdh
-
ns
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Delay from Supply Voltage Stable to Control Port Ready
-
-
ns
(Note 10)
(Note 11)
(Note 11)
ns
tr2
100
100
-
ns
tf2
-
ns
tdpor
100
µs
Notes: 9. tspi is only needed before first falling edge of CS after power is applied. tspi = 0 at all other times.
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For f
< 1 MHz.
cclk
VD
tdpor
CS
tspi tcss
tscl tsch
tcsh
CCLK
tr2
t f2
CDIN
tdsu
tdh
Figure 3. Control Port Timing - SPI Format (Write Only)
DS759F1
9
CIRRUS [ CIRRUS LOGIC ]
