CS2100-OTP
example of how to determine the range of RefClk frequencies around 12 MHz to be used in order to
achieve the lowest jitter PLL output at a frequency of 12.288 MHz is as follows:
fL ≤ fRefClk ≤ fH where:
CLK__OUT Jitter
180
*32/N
f
CLK__OUT
160
140
120
100
80
31
32
fL = fCLK_OUT × ----- + 15kHz
= 12.288MHz × 0.96875 + 15kHz
= 11.919MHz
-15 kHz
+15 kHz
and
60
32
32
fH = fCLK_OUT × ----- – 15kHz
40
= 12.288MHz × 1 + 15kHz
20
-80
-60
-40
-20
0
20
40
60
80
= 12.273MHz
Normalized REF__CLK Frequency (kHz)
Figure 8. REF_CLK Frequency vs a Fixed CLK_OUT
Referenced Control
Parameter Definition
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 21
5.2.2
Crystal Connections (XTI and XTO)
An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode par-
allel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 9. As shown,
nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer
to the “AC Electrical Characteristics” on page 7 for the allowed crystal frequency range.
XTI
XTO
40 pF
40 pF
Figure 9. External Component Requirements for Crystal Circuit
5.2.3
External Reference Clock (REF_CLK)
For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the
reference clock source and XTO should be left unconnected or terminated through a 47 kΩ resistor to
GND.
5.3
Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used by the Digital PLL and Fractional-N Logic block to
dynamically generate a fractional-N value for the Frequency Synthesizer (see “Hybrid Analog-Digital PLL”
on page 10). The Digital PLL first compares the CLK_IN frequency to the PLL output. The Fractional-N logic
block then translates the desired ratio based off of CLK_IN to one based off of the internal timing reference
12
DS841F1
CIRRUS [ CIRRUS LOGIC ]
