CS2100-CP
5.3.3
Effective Ratio (R
)
EFF
The Effective Ratio (R
) is an internal calculation comprised of R and the appropriate modifiers, as
EFF
UD
previously described. R
is calculated as follows:
EFF
R
= RUD • R
EFF
MOD
To simplify operation the device handles some of the ratio calculation functions automatically (such as
when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need
to be altered to account for internal dividers.
Ratio modifiers which would produce an overflow or truncation of R
should not be used; For example
EFF
if R is 1024 an R
of 8 would produce an R
value of 8192 which exceeds the 4096 limit of the
UD
MOD
EFF
12.20 format. In all cases, the maximum and minimum allowable values for R
are dictated by the fre-
EFF
quency limits for both the input and output clocks as shown in the “AC Electrical Characteristics” on
page 7.
5.3.4
Ratio Configuration Summary
The R is the user defined ratio stored in the register space. The resolution for the R is selectable by
UD
UD
setting LFRatioCfg. R-Mod is applied if selected. The user defined ratio, and ratio modifier make up the
effective ratio R , the final calculation used to determine the output to input clock ratio. The effective
EFF
ratio is then corrected for the internal dividers. The conceptual diagram in Figure 17 summarizes the fea-
tures involved in the calculation of the ratio values used to generate the fractional-N value which controls
the Frequency Synthesizer.
RefClkDiv[1:0]
Timing Reference Clock
Divide
(XTI/REF_CLK)
Frequency
Synthesizer
PLL Output
SysClk
Effective Ratio REFF
N
RModSel[2:0]
RefClkDiv[1:0]
Ratio Format
User Defined Ratio RUD
12.20
20.12
Ratio
Modifier
Digital PLL &
Fractional N Logic
Ratio
R Correction
LFRatioCfg
Frequency Reference Clock
(CLK_IN)
Figure 17. Ratio Feature Summary
Referenced Control
Register Location
Ratio......................................“Ratio (Address 06h - 09h)” on page 27
LFRatioCfg............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 29
RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 26
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 28
DS840F1
19
CIRRUS [ CIRRUS LOGIC ]
