CS2100-CP
5.1.2
Crystal Connections (XTI and XTO)
An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode par-
allel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 11. As shown,
nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer
to the “AC Electrical Characteristics” on page 7 for the allowed crystal frequency range.
XTI
XTO
40 pF
40 pF
Figure 11. External Component Requirements for Crystal Circuit
5.1.3
External Reference Clock (REF_CLK)
For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the
reference clock source and XTO should be left unconnected or pulled low through a 47 kΩ resistor to
GND.
5.2
Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used by the Digital PLL and Fractional-N Logic block to
dynamically generate a fractional-N value for the Frequency Synthesizer (see “Hybrid Analog-Digital PLL”
on page 12). The Digital PLL first compares the CLK_IN frequency to the PLL output. The Fractional-N logic
block then translates the desired ratio based off of CLK_IN to one based off of the internal timing reference
clock (SysClk). This allows the low-jitter timing reference clock to be used as the clock which the Frequency
Synthesizer multiplies while maintaining synchronicity with the frequency reference clock through the Digital
PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Characteristics” on page 7.
5.2.1
CLK_IN Skipping Mode
CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses
for up to 20 ms (t ) at a time (see “AC Electrical Characteristics” on page 7 for specifications). CLK_IN
CS
skipping mode can only be used when the CLK_IN frequency is below 80 kHz and CLK_IN is reapplied
within 20 ms of being removed. The ClkSkipEn bit enables this function.
14
DS840F1
CIRRUS [ CIRRUS LOGIC ]
