CS2100-CP
8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 27
8.5 Ratio (Address 06h - 09h) .............................................................................................................. 27
8.6 Function Configuration 1 (Address 16h) ........................................................................................ 28
8.6.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 28
8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 28
8.6.3 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 28
8.7 Function Configuration 2 (Address 17h) ........................................................................................ 29
8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 29
8.7.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 29
8.8 Function Configuration 3 (Address 1Eh) ........................................................................................ 29
8.8.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 29
9. CALCULATING THE USER DEFINED RATIO .................................................................................... 30
9.1 High Resolution 12.20 Format ....................................................................................................... 30
9.2 High Multiplication 20.12 Format ................................................................................................... 30
10. PACKAGE DIMENSIONS .................................................................................................................. 31
THERMAL CHARACTERISTICS ......................................................................................................... 31
11. ORDERING INFORMATION .............................................................................................................. 32
12. REFERENCES .................................................................................................................................... 32
13. REVISION HISTORY .......................................................................................................................... 32
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5
Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 8
Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 8
Figure 4. CLK_IN Random Jitter Rejection and Tolerance ......................................................................... 8
Figure 5. Control Port Timing - I²C Format .................................................................................................. 9
Figure 6. Control Port Timing - SPI Format (Write Only) .......................................................................... 10
Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 11
Figure 8. Hybrid Analog-Digital PLL .......................................................................................................... 12
Figure 9. Internal Timing Reference Clock Divider ................................................................................... 13
Figure 10. REF_CLK Frequency vs a Fixed CLK_OUT ............................................................................ 13
Figure 11. External Component Requirements for Crystal Circuit ............................................................ 14
23
Figure 12. CLK_IN removed for > 2 SysClk cycles ................................................................................ 15
23
Figure 13. CLK_IN removed for < 2 SysClk cycles but > t
CS .................................................................................. 15
Figure 14. CLK_IN removed for < t
CS .................................................................................................................................. 16
Figure 15. Low bandwidth and new clock domain .................................................................................... 17
Figure 16. High bandwidth with CLK_IN domain re-use ........................................................................... 17
Figure 17. Ratio Feature Summary ........................................................................................................... 19
Figure 18. PLL Clock Output Options ....................................................................................................... 20
Figure 19. Auxiliary Output Selection ........................................................................................................ 20
Figure 20. Control Port Timing in SPI Mode ............................................................................................. 22
Figure 21. Control Port Timing, I²C Write .................................................................................................. 23
Figure 22. Control Port Timing, I²C Aborted Write + Read ....................................................................... 23
LIST OF TABLES
Table 1. Ratio Modifier .............................................................................................................................. 18
Table 2. Example 12.20 R-Values ............................................................................................................ 30
Table 3. Example 20.12 R-Values ............................................................................................................ 30
DS840F1
3
CIRRUS [ CIRRUS LOGIC ]
