欢迎访问ic37.com |
会员登录 免费注册
发布采购

CS2000-CP 参数 Datasheet PDF下载

CS2000-CP图片预览
型号: CS2000-CP
PDF下载: 下载PDF文件 查看货源
内容描述: 小数N分频时钟合成器与时钟乘法器 [Fractional-N Clock Synthesizer & Clock Multiplier]
分类和应用: 时钟
文件页数/大小: 36 页 / 425 K
品牌: CIRRUS [ CIRRUS LOGIC ]
 浏览型号CS2000-CP的Datasheet PDF文件第2页浏览型号CS2000-CP的Datasheet PDF文件第3页浏览型号CS2000-CP的Datasheet PDF文件第4页浏览型号CS2000-CP的Datasheet PDF文件第5页浏览型号CS2000-CP的Datasheet PDF文件第6页浏览型号CS2000-CP的Datasheet PDF文件第7页浏览型号CS2000-CP的Datasheet PDF文件第8页浏览型号CS2000-CP的Datasheet PDF文件第9页  
CS2000-CP
Fractional-N Clock Synthesizer & Clock Multiplier
Features
Delta-Sigma Fractional-N Frequency Synthesis
– Generates a Low Jitter 6 - 75 MHz Clock
from an 8 - 75 MHz Reference Clock
Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to
30 MHz Clock Source
Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM in High-
Resolution Mode
I²C
®
/ SPI™ Control Port
Configurable Auxiliary Output
Flexible Sourcing of Reference Clock
– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal
Minimal Board Space Required
– No External Analog Loop-filter
Components
General Description
The CS2000-CP is an extremely versatile system
clocking device that utilizes a programmable phase
lock loop. The CS2000-CP is based on a hybrid ana-
log-digital PLL architecture comprised of a unique
combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for both frequency synthesis/clock generation from a
stable reference clock as well as generation of a low-
jitter clock relative to an external noisy synchronization
clock. The design is also unique in that it can generate
low-jitter clocks relative to noisy external synchroniza-
tion clocks at frequencies as low as 50 Hz. The
CS2000-CP supports both I²C and SPI for full software
control.
The CS2000-CP is available in a 10-pin MSOP pack-
age in Commercial (-10°C to +70°C) grade. Customer
development kits are also available for device evalua-
tion. Please see
for
complete details.
3.3 V
Timing Reference
Frequency Reference
PLL Output
Lock Indicator
I²C/SPI
Software Control
I²C / SPI
Auxiliary
Output
8 MHz to 75 MHz
Low-Jitter Timing
Reference
Fractional-N
Frequency Synthesizer
6 to 75 MHz
PLL Output
Output to Input
Clock Ratio
N
50 Hz to 30 MHz
Frequency
Reference
Digital PLL & Fractional
N Logic
Output to Input
Clock Ratio
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
©
Cirrus Logic, Inc. 2008
(All Rights Reserved)
JUN '08
DS761PP1